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| CMX635 isdn subscriber processor ? 2001 consumer microcircuits limited d/635/2 december 2001 advance information features applications s/t interface to itu - t i.430 (te & nt1) isdn terminal equipment 2b + 1d - channel hdlc controllers isdn intelligent nt?s iom? - 2 / gci interface isdn phones and feature phones selectable a - law/ - law pcm codec digital & analogue answer - phones 100mw speaker - phone output data adaptors 2 independent analogue inputs active and passive terminal adaptors pre - pro grammed tone generators alarm systems v.23/bell 202 fsk generator point - of - sale terminals ringing signal and spm generators ?group 4? fax equipment dtmf encoder/decoder video phones iom is a trademark of siemens ag. 1.1 brief desc ription the CMX635 is an integrated subscriber processor designed for low chip - count isdn voice/data terminals and pots terminal adaptors. its functions facilitate operation in an isdn feature phone with speakerphone capability or in a pots terminal adapt er with subscriber pulse metering (spm), dtmf encoder/decoder, caller line id (clid) and caller id on call waiting (cidcw) capabilities. it also implements many functions needed in an intelligent nt or nt1plus system. the CMX635 incorporates a 4 - wire st interface conforming to itu - t i.430 and ets 300 012 - 1 specifications. hdlc controllers and associated fifos are provided for b1, b2 and d - channel s, which can be configured to automatically process the bit stuffing, flag generation/recognition, address mat ching and crc generation/checking required to support the itu q.921 protocol. an iom - 2 tm /gci interface is provided to enable operation with other iom compliant devices. the m controller interface is compatible with multiplexed and non - multiplexed addres s/data busses and generic motorola and intel style control. the CMX635 will automatically detect which style of interface is being used and configure itself accordingly. the device is available in a 48 - pin tqfp package and has progressive powersave modes to aid low power operation.
isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 2 d/635/2 contents section page 1.1 brief description ................................ ................................ ................................ .... 1 1.2 CMX635 block diagrams ................................ ................................ ....................... 4 1.2.1 functional block diagram ................................ ................................ .................. 4 1.2.2 analogue block diagram ................................ ................................ .................... 5 1.3 signal list ................................ ................................ ................................ .............. 6 1.3.1 pin numbers ................................ ................................ ................................ ....... 6 1.3.2 pin description ................................ ................................ ................................ ... 7 1.4 external compone nts ................................ ................................ .......................... 10 1.4.1 component values ................................ ................................ ........................... 11 1.4.2 equivalent analogue input/output circuits ................................ ....................... 12 1.5 functional description ................................ ................................ ........................ 13 1.5.1 the st interface and digital phase locked loop ................................ ............. 14 1.5.2 the hdlc controllers and fifos ................................ ................................ .... 15 1.5.3 the iom interface ................................ ................................ ............................ 17 1.5.4 the g.711 codec and analogue gain path ................................ ...................... 19 1.5.5 the tone generator and tone decoder ................................ ........................... 19 1.5.6 the channel routing block ................................ ................................ .............. 20 1.5.7 speaker phone functions ................................ ................................ ................ 20 1.5.8 the processor interface, top level status and power control ......................... 21 1.6 programming guide. ................................ ................................ ........................... 23 1.6.1 interrupt structure ................................ ................................ ............................ 23 1.6.2 CMX635 register definition and description ................................ .................... 25 1.6.2.1 st interf ace block ................................ ................................ ....................... 25 1.6.2.2 data routing block ................................ ................................ ..................... 31 1.6.2.3 hdlc fifo control ................................ ................................ ..................... 33 1.6.2.4 hdlc rx channel control ................................ ................................ .......... 36 1.6.2.5 hdlc tx channel control ................................ ................................ ........... 40 1.6.2.6 iom interface control ................................ ................................ .................. 42 1.6.2.7 clock and power control ................................ ................................ ............. 45 1.6.2.8 speaker phone statistics ................................ ................................ ............ 49 1.6.2.9 audio bloc k ................................ ................................ ................................ . 52 1.6.2.10 tone/codec block ................................ ................................ ....................... 56 1.6.3 register address definition summary ................................ .............................. 63 1.7 application notes ................................ ................................ ................................ 67 1.7.1 example CMX635 configurations ................................ ................................ .... 67 1.7.1.1 dual short loop pots system ................................ ................................ ... 67 1.7.1.2 isdn telephone/feature/speaker phone. ................................ ................... 68 1.7.1.3 isdn pc card (active data adaptor) ................................ .......................... 69 1.7.1.4 video phone ................................ ................................ ............................... 70 1.7.1.5 intelligent nt or nt1plus ................................ ................................ ............ 71 1.7.2 iom - 2 interface summary ................................ ................................ ................ 72 1.7.2.1 general ................................ ................................ ................................ ....... 72 1.7.2.2 frame structure ................................ ................................ .......................... 72 1.7.2.3 monitor channel handshake protocol ................................ .......................... 74 1.7.2.4 c/i0 channel description ................................ ................................ ............. 76 1.7.2.5 tic bus description ................................ ................................ .................... 76 1.7.3 tone switching ................................ ................................ ................................ 79 1.7.4 telecom tones ................................ ................................ ................................ 80 1.8 performance specification ................................ ................................ .................. 84 1.8.1 electrical performance ................................ ................................ ..................... 84 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 3 d/635/2 1.8.1.1 absolute maximum ratings ................................ ................................ ......... 84 1.8.1.2 operating limits ................................ ................................ .......................... 84 1.8.1.3 operating characteristics ................................ ................................ ............ 85 1.8.2 packaging ................................ ................................ ................................ ........ 96 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 4 d/635/2 1.2 CMX635 block diagrams 1.2.1 functional block diagram the diagram b elow shows the main elements of the CMX635. figure 1. CMX635 block diagram analog switching ring gen. dtmf decode dtmf encode codec + tone gen. sp phone stats channel routing iom interface xtal osc. s/t interface b2 chan hdlc b1 chan hdlc d chan hdlc status microprocessor interface bias gen. lin1 lin2 lout1 lout2 x1 x2 iom vbias cs rd wr ale addr dat/ add dtack int dpll por reset rx1p rx1n rx2p rx2n tx1on tx1o tx2o tx2on tx1op tx1n rx1o 8 vdd(a) vdd(d) vss(d) x2 vss(a) x2 rx2o clk out rx1 and rx2 chann els used for mic or pots input. tx1 channel used for earpiece or pots output. tx2 channel used for loudspeaker or pots ring output. for clarity, internal processor bus not shown. fsk encode set i spm gen. spm hdlc fifo isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 5 d/635/2 1.2.2 analogue block diagram notes: g1 = 0db to 22.5db ( in 1.5db steps) - level set/agc gain. g2 = 0db to ? 42db (in 3db steps + mute) - speakerphone attenuation. g3 = +6db to ? 42db (in 0.5db steps + mute) - speaker/ring output gain. g4 = 0db to ? 42db (in 3db steps + mute) - tone gain g5 = - 6db to ? 36db (in 2db steps) - sidetone gain. s1 ? s8 = user selectable switches. is1 = internally operated switches (shown for inform ation only). t1 - t2 = test switches (shown for information only). at reference points ?a? and ?b? the nominal signal level scaling as defined in itu - t g714 is: 0dbm0 o 0dbm = 775 mv r.m.s. at 5v power supply. the maximum unclipped sine wave possibl e on reference points ?a? and ?b? is: 3.14dbm0 o 3.14dbm = 1.11 v r.m.s. for a law companding at 5 v supply. peak to peak full scale input signal to rx codec is 0.986 x v dd for a - law companding, and 0.989 x v dd for m - law companding. figure 2. analogue block d iagram sidetone b chan rx dat b chan tx dat f2 ( - 3.9db) f1 (+3.9db) s5 s4 dtmf decode rx2o tx1o tx1on tx1n rx1n tx1op rx1p rx1o s1 data g1 tone generator tx codec rx codec amplitud e stats amplitude stats fsk uart rx2n rx2p gx = programmable gain sx = user switch isx = internal switch fx = filter tx = test switch tx2on tx2o s2 s3 g3 data ring generator tone voice data g4 data g2 tone voice data data data data g5 data data data t1 t2 s7 is1 a b spm generator data spm ring - 3db s6 s8 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 6 d/635/2 1.3 signal list 1.3.1 pin numbers the following table lists the complete pin description of the CMX635 48 - pin tfqp (l4) package. pin # name type function 30 sttxp ana st interface transmit output - positive 31 sttxn ana st interface transmit output - nega tive 27 strxp ana st interface receive input - positive 28 strxn ana st interface receive input - negative 42 dcl i t /o c iom - 2 interface data clock 41 fsc i t /o c iom - 2 interface frame sync 43 iomtx o/d, i t iom transmit output - dd when upstream device ? note 1 44 iomrx i t , o/d iom receive input - du when upstream device ? note 1 7 ad0 i c /o c processor address/data bus bit 0 (lsb) 6 ad1 i c /o c processor address/data bus bit 1 5 ad2 i c /o c processor address/data bus bit 2 4 ad3 i c /o c processor address/dat a bus bit 3 3 ad4 i c /o c processor address/data bus bit 4 2 ad5 i c /o c processor address/data bus bit 5 1 ad6 i c /o c processor address/data bus bit 6 48 ad7 i c /o c processor address/data bus bit 7 (msb) 14 asel i c address select 9 dtack o/d data acknowl edge 15 ale i c address latch enable (as in motorola style applications) 12 nwr i c write strobe (rd/nwr or e in motorola style applications) 11 nrd i c read strobe (ds in motorola style applications) 13 ncs i c chip select 8 nirq o/d interrupt request 16 reset i c chip reset 46 x1 ana crystal (or oscillator) input 45 x2 ana crystal input 2 47 clkout o c clock out - buffered master clock 18 vbias ana internal bias. 23 rx1o ana analogue input amplifier #1 output 24 rx1p ana analogue input amplifier # 1 positive input 25 rx1n ana analogue input amplifier #1 negative input 20 rx2o ana analogue input amplifier #2 output 21 rx2p ana analogue input amplifier #2 positive input 22 rx2n ana analogue input amplifier #2 negative input 38 tx1op ana output #1 raw output 36 tx1o ana output amplifier #1 positive output - earpiece/pots 35 tx1on ana output amplifier #1 negative output - earpiece/pots 37 tx1n ana output amplifier #1 negative input 34 tx2o ana output amplifier #2 positive output - loudspeaker/ri ng 33 tx2on ana output amplifier #2 negative output - loudspeaker/ring 17 spm ana subscriber pulse metering output 29 stiset ana st tx current limit set 39 vdda s positive analogue supply, 2.7 - 5 v 26 vdda s positive analogue supply, 2.7 - 5 v 32 vs sa s analogue gnd 19 vssa s analogue gnd 40 vddd s positive digital supply, 2.7 - 5 v 10 vssd s digital gnd isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 7 d/635/2 pin type legend: i - digital input o - digital output i/o - digital bi - directional o/d - open drain ana - analogue input or output subscript d enotes input/output levels c - cmos t - ttl note 1: iomrx normally ttl input but can become open drain output during bus reversal. iomtx normally open drain output but can become ttl input during bus reversal. 1.3.2 pin description sttxp, sttxn st bus diff erential transmit outputs. upstream data in te configuration and downstream data in nt configuration. the nominal amplitude is 2.1v differential with 280 load which equates to 750mv at the st interface when the recommended line transformer is used. sttx p is positive with respect to sttxn for transmission of the frame pulse bit. note: particular care should be taken to avoid electro - static discharge damage to these pins as the unpowered impedance requirements result in reduced internal protection. strxp , strxn st bus differential receive inputs. downstream data in te configuration and upstream data in nt configuration. the nominal expected differential pulse amplitude is 1.2v which equates to 750mv at the st interface with recommended components . ampli tudes down to 255mv at the st interface can be accommodated while signal activity above 100mv will generate a ?wake - up? interrupt if required. polarity need only be maintained for point to multipoint configurations. dcl iom - 2 interface ?terminal? mode dat a clock operating at a nominal frequency 1.536mhz. the dcl can be configured as an output (cmos levels) in timing master mode or as an input (ttl levels) in timing slave mode. dcl operates at twice the iom bit rate and is used to sample the data on the iom receive input. fsc iom - 2 interface frame sync operating at a nominal frequency of 8khz. the fsc can be configured as an output (cmos levels) in timing master mode or as an input (ttl levels) in timing slave mode. the rising edge of fsc defines the start of an iom frame and is nominally synchronous with the rising edge of dcl. iomtx, iomrx iom - 2 interface transmit and receive data pins operating at a nominal bit rate of 768kbps. the iomtx pin equates to the iom dd (data downstream) signal when the CMX635 is the upstream device (te configuration) and to the iom du (data upstream) signal when the CMX635 is the downstream device (nt configuration). the iomtx pin can be configured as open drain or active cmos level output. the direction of the iomtx and iomrx pins can be reversed for certain channels in the iom frame. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 8 d/635/2 ad[7:0] processor interface address/data bus. bi - directional cmos level input/output bus that carries multiplexed address and data when multiplexed mode is automatically detected by the CMX635 a nd data only when non - multiplexed mode is detected. asel address select. asel, when asserted, selects the internal indirect address register as the destination for non - multiplexed processor read/writes, or the data register when de - asserted. asel may be c onnected to a[0] of the non - multiplexed processor address bus. connect to vss for multiplexed interface operation. dtack data acknowledge. active only when the motorola style multiplexed mode processor interface is detected. it is an open drain output tha t is pulled low at the start of a processor read or write cycle and remains low until the CMX635 internal cycle is complete. the dtack signal can be used to implement a hardware handshake cycle timing mechanism. ale address latch enable. the multiplexed a ddress from the ad bus is latched on the falling edge of ale. connect ale to vcc if an intel style non - multiplexed interface is being used and to vss for a motorola style non - multiplexed interface. nwr write strobe, active low. latches the data from the a d bus on the rising edge in intel style mode. acts as a r/nw strobe in motorola mode. see the timing diagrams in section 1.8.1 for more details on the nwr pin function. nrd read strobe, active low. initiates a CMX635 read cycl e and enables read data to be driven onto the ad bus in intel style mode. acts as a ds or e strobe in motorola style mode. see the timing diagrams in section 1.8.1 for more details on the nwr pin function. ncs chip select, act ive low. must be low for duration of read or write cycle in all interface modes. processor interface is inactive and will not respond to read/write strobe activity when ncs is high. nirq interrupt request, open drain. pulled to vss when the CMX635 interna l status register s generate an unmasked interrupt request. it remains in its high impedance state when no interrupts are pending. an external pull - up resistor is required. reset global chip reset. active high reset input resets CMX635 internal state and r estores default configuration. the reset input should be asserted at power - up before any configuration is written or modes activated. the reset must be asserted until the oscillator input has stabilised (either from a crystal or external clock source) to e nsure full internal reset. x1, x2 oscillator input pins. a 12.288mhz or 15.36mhz crystal may be connected between these pins (see external components section 1.4 ) or an external clock source may be connected to x1 with x2 conn ected to vss. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 9 d/635/2 clockout buffered clock. a buffered version of the input clock on x1 is available on clockout and may be used for driving the clock inputs of other devices. optionally the internal phase locked 1.536mhz clock may be routed to clockout, whic h can be utilised by external circuitry to lock together multiple CMX635 devices if required. vbias the internal analogue reference voltage. an external capacitor must be connected between vbias and analogue ground to ensure noise free operation. rx1o, r x1p, rx1n, rx2o, rx2p, rx2n output, positive and negative inputs of the differential microphone input amplifiers. see section 1.4.2 for details of the equivalent analogue input circuits. tx1o, tx1on, tx1n, txop differential ou tputs, negative input and internal preamplifier output of the earpiece/pots output amplifier. see section 1.4.2 for details of the equivalent analogue output circuits. the required external gain components are inserted between the tx1on and tx1n pins, which form the input impedance to the inverting earpiece amplifier. tx2o, tx2on loudspeaker/ring amplifier differential outputs. spm subscriber pulse metering sine wave output for emulating pots style call cost information. stis et st transmitter current set pin. a fixed resistor must be connected between this pin and analogue vss to ensure accurate current limit on the st transmitter. vssd, vddd, vssa, vdda analogue and digital supply pins. ensure adequate high and low frequency decoupling between positive and negative supplies. it is recommended that the analogue and digital supplies are locally separated. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 10 d/635/2 1.4 external components 10 8 48 9 11 12 3 1 2 4 5 7 6 29 31 30 28 27 25 26 36 35 34 32 33 47 45 44 43 46 42 41 39 38 37 40 13 14 16 17 18 15 19 20 22 23 24 21 strxn strxp vdda vssa vssa c2 r5 r1 c1 r2 r3 c3 c4 r4 vssa c5 rx2o vbias rx2n rx1o rx1n sttxn sttxp ad3 r6 c6 r7 stiset tx1op tx1n vdda vddd x1 x2 rx tx tx1o tx1on tx2on tx2o rx1in rx2in r10 r11 r8 r9 ad6 clockout ad5 ad2 ad1 ad0 ad4 processor address/data bus ad7 fsc iomtx(dd) dcl iomrx(du) nirq nwr vssd dtack nrd ncs asel reset ale spm vddd vddd vddd vdda vssa vssd supply ground c12 c13 c10 c11 CMX635 t1 c7 xt1 c8 c9 vssd figure 3. recommended external components isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 11 d/635/2 1.4.1 component values xt1 12.288mhz o r 15.36mhz t1 line transformer, 2:1 turns ratio i.e. etal p3024 ? note 1. r1, r3 note 2. r2, r4 110k w 1% r5 15 k w 2% r6 note 3. r7 39k w 1% r8, r9 10k w 5% r10, r11 750r (5v supply), 5% 470r (3.3v supply) 5% c1, c3, c5 1.0 m f 5% c2, c 4 220pf 5% c6 150pf 5% c7 27nf 5% c8, c9 33pf 20% c10, c12 1.0 m f 10% c11, c13 10nf 10% - note 4. notes: 1 . if a suitable transformer module is not used, protection components should be added around the line transformers, including 33r s eries resistors in the sttx lines and 10k w series resistors in the strx lines. 2 . r1, r2, c1 and c2 form the gain components of input amplifier rx1. r3, r4, c3 and c4 form the gain components of input amplifier rx2. r1 and r3 should be chosen as required by the input signal level according to the following formula: gain = - r2/r1 or - r4/r3 c1, r1 and c3, r3 should be chosen so as not to compromise the low frequency performance. 3 . r6, r7, c6 and c7 form the gain components of output amplifier tx1. r6 sh ould be chosen to give the required output signal level according to the following formula: gain = - r7/r6 4 . ensure that high frequency filter capacitors are placed physically close to appropriate power pins. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 12 d/635/2 1.4.2 equivalent analogue input/output circuits figure 4. equivalent input/output circuits c2 r2 r6 c6 r7 tx1o r1 c1 rx1in tx1n tx1op vbias - + vbias + - tx1on vbias + - rx1p rx1n rx1o c4 r4 r3 c3 rx2in vbias + - rx2p rx2n rx2o receive 1 equivalent input transmit 1 equivalent output receive 2 equivalent input c7 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 13 d/635/2 1.5 functional description the CMX635 is a highly integrated isdn subscriber processor that allows low chip count systems to be designed for a wide variety of isdn voice/data terminals and pots terminal adaptors. it can also provide the majority of functions required to implement an intelligent nt or nt1plus system. the CMX635 incorporates a 4 - wire st interface, which conforms fully to the itu - t i.430 and ets 300 012 - 1 specifications. it provides the necessary layer - 1 control to implement both the te and nt ends of the st reference point and the layer - 2 controls to implement the d - channel signalling layer. hdlc controllers and associated fifos are provided for the b1, b2 and d - channel s. the controllers can be configured to automatically process the bit stuffing, flag generation/recognition, address matching and crc generation/checking required to support the itu q.921 protocol reducing the software overhead on the host processor. the a utomatic processing can be progressively disabled until fully transparent operation is achieved with corresponding increased processor load. the data fifos are implemented as a 1024 byte ram that can be flexibly partitioned to form the 6 required fifos (2b +d, receive and transmit), enabling optimum fifo size to be selected for the application. an iom - 2 tm /gci interface is provided to enable operation with other iom compliant devices. this facility can be used to connect to a ?u? interface device in nt mode of operation or to expand the number of pots ports in te mode by connection to devices such as the cmx625 ? isdn ta pots interface. the iom interface can be configured as a timing master or slave for te or nt applications respectively and has full mult - fr aming capabilities. the CMX635 has the functions necessary for operation as an isdn feature phone with speakerphone capability or as a pots terminal adapter. there are 2 independent uncommitted differential input amplifiers suitable for connection to 2 mi crophones for feature - phone applications or to a slic/pots hybrid for pots operation. a 100mw power amplifier is provided to drive a speaker for feature - phones or the ring input to a slic for pots. an additional output is provided to drive a handset earpie ce or the slic/hybrid input for pots. sophisticated speakerphone operation can be implemented using the digital noise and voice filters available in the CMX635 in conjunction with user supplied software algorithms. for pots operation a dtmf decoder enabl es interpretation of dialling information and can also be configured to detect far end dtmf tones. a tone generator supplies all of the necessary tone frequencies for call progress tones. other tone standards supported are: fax and modem ?answer? and ?orig inate?, itu (ccitt) ?r1? and ?r2? signals, and sufficient tones for simple melody generation. caller line id (clid) and caller id on call waiting (cidcw) functionality can be emulated using the tone generator and the fsk uart facility. a subscriber p ulse metering (spm) output is provided to enable operation with pots legacy payphone equipment. the frequency standard can be set to either 12khz or 16khz. a dtmf generator is available to allow feature - phone equipment to generate comfort dial tones and to enable control of remote dtmf signalling and menuing systems. the m controller interface is compatible with multiplexed and non - multiplexed address/data busses and generic motorola and intel style control. the CMX635 will automatically detect which sty le of interface is being used and configure itself accordingly. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 14 d/635/2 the CMX635 is highly configurable, via internal software accessible registers, to operate in a wide variety of applications. the details of every configuration and status register are describ ed in the programming guide section 1.6 . the main functions of the CMX635 are shown in the block diagrams and are conceptually: the st interface and digital phase locked loop the hdlc controllers and fifos the iom interface th e g.711 codec and analogue gain path the tone generator and tone decoder the channel routing block speaker phone functions the processor interface, top level status and power control 1.5.1 the st interface and digital phase locked loop the st interface performs the following functions: s/t bus activation/deactivation control clock and data recovery frame synchronisation d - ch annel access multi - frame generation/reception the activation/deactivation control when configured in te mode follows closely the itu - t i.43 0 requirements and is mainly autonomous (timer t3 requiring implementation in software). the activation states are advanced through automatic detection of the info0, info2 and info4 signals on the receive bus and are initiated by software writes of the act ivate and deactivate request primitives and the power up/down status. note that although the itu specification provides no facility for the st bus to be deactivated directly by the te, the deactivate request control is provided to allow implementation of t imer t3 in software. the st activation state can be read by software and the detection of the various info signals can be configured to generate an interrupt if required. the activation status indicators ?connect indication?, ?activate indication? and ?err or indication? are available to the software and may also be configured to generate an interrupt request if required. the st interface autonomously outputs the ?info0?, ?info1? and ?info3? signals at the appropriate states of activation/deactivation. for nt mode of operation, the next state is under software control and is written directly to the st interface. the detection of ?info0?, ?info1? and ?info3? is available to the software to enable next state calculation. the data recovery function consists o f an analogue section and a digital section. the analogue st receiver continuously tracks the amplitude of the incoming signal and uses an adaptive slicing level to recover digital data from the 3 level receiver input. the data is coded into positive pulse , negative pulse or no pulse. the digital section over - samples the recovered data and performs a majority decision algorithm to determine the correct recovered bit stream. the clock recovery function consists of a digital phase - locked loop that tracks the raw sampled data in te mode to produce a filtered and frequency locked master sample clock at a nominal 192khz. this clock is used to sample the recovered receive bit stream and to generate a phase locked st transmit clock. in nt mode the st bit clock tra cks the received iom fsc signal thus maintaining network synchronisation. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 15 d/635/2 the frame synchronisation function detects the correct occurrence of framing and auxiliary framing pulses and in te mode adjusts the receive and transmit frames accordingly. two con secutive correctly received frames are required before the interface is designated as frame locked. d - channel access in te mode is initiated by writing the ?data request? primitive to the CMX635 along with the required primary priority level. the primary priority can be set to 8 for signalling frames and to 10 for data frames. the d - channel access function will then ensure that the d - channel is available by monitoring the number of consecutive d - channel echo bits that are set to binary 1. if the count reac hes the level defined by the priority, the d - channel hdlc block is allowed to transmit. if an echo bit is received that does not match the transmitted d bit, the d - channel is released and a ?collision? status flag is set. a ?data indication? primitive can be configured to generate an interrupt when the d - channel has been successfully acquired. after transmission of an hdlc frame, and if another frame is pending, the priority is automatically decreased (8 to 9 and 10 to 11) to allow other te devices access t o the d - channel. if multiple d - channel transmission frames are set up in the hdlc fifo (see section 1.5.2 ) the access mechanism will automatically allow other te?s access to the d - channel between frames but will remain active until all frames are sent. d - channel access in intelligent nt mode uses a similar access mechanism to te mode but the d bits from the downstream te?s are used to determine d - channel activity instead of the echo bits. when an nt has successf ully acquired the d - channel it sets the echo bits to the downstream te?s to binary 0, thus inhibiting te d - channel access. the CMX635 supports full st multi - framing capability and in te mode will synchronise to incoming multi - frame markers. in nt mode for matted multi - frames are generated. the CMX635 is capable of processing 1 ?q? channel and ?5? s channels as defined in itu - t i.430. full sets of interruptible status flags are available to indicate when the transmit/receive data buffers require servicing. 1.5.2 the hdlc controllers and fifos the CMX635 contains flexible controllers and fifos for both b - channels and the d - channel that can be individually selected and enabled. the main functions of the hdlc controllers and fifos are: flag generation/recognition bi t stuffing/destuffing and octet alignment address field matching crc generation/checking re - configurable fifo data buffers on all transmit and receive channels multiple hdlc frame generation and reception the CMX635 will automatically generate the 01111110 b sequence defined as an hdlc flag at the beginning of each new frame. reception of an hdlc frame will initiate the frame receive sequence and the reception of a second flag will be interpreted as the end of an hdlc frame. ?shared? flags (1 flag between th e end of a frame and the start of a new frame) will be processed correctly in the receive channel. in the b transmit channels a ?shared? flag can optionally be used between multiple frames. the bit stuffing and de - stuffing requirements of the hdlc protocol are automatically implemented unless the fully transparent modes of operation are selected. if transparent receive mode for a b - channel is selected, the serial bit stream is formed directly into octets and written to the receive fifo. transparent receive mode is not available in the d - channel. if transparent transmit mode is selected, the data from the fifo is read in octets and transmitted directly as a serial bit stream octet aligned with the st frame b - channel octets. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 16 d/635/2 the address field matching functio n can be used in the d - channel to match incoming sapi and tei identifiers automatically. when address matching is turned on, incoming data frames are ignored unless the required address fields match the pre - programmed values. 4 independent match addresses can be programmed for each of the 1 st and 2 nd address fields as well as the broadcast addresses for both fields. the extent of address matching required can be selected to be zero, one or both fields. the combination of the pre - programmed match registers t o be used is also programmable. a successful address match will set an interruptible status bit. if address matching is turned off, all incoming frames are routed to the receive fifo irrespective of address values and the software must determine if the fra me is relevant. for transmit frames, either 1 or 2 address registers may be prepended to the transmit fifo data automatically unless user address mode is selected, in which case the address fields must be written to the fifo as part of the data frame by software. the CMX635 can automatically generate and decode the16 bit crc fields appended to the end of hdlc frames and for received frames will generate an interruptable good packet or crc error status as appropriate. if automatic crc handling is not requ ired, the transmit crc value can be supplied by the user and written as the last data octet(s) to the fifo. for received frames the crc value available as the last octet(s) in the receive fifo can be decoded in software. if automatic crc generation is enab led, a facility is provided to force a crc error for purposes of system test/checks. status flags are provided to indicate a number of abnormal conditions, which can be configured to generate interrupt requests. the conditions indicated are: received crc error received octet mis - alignment (frame not an integer number of octets) received packet aborted (7 consecutive binary 1?s received) received short packet (frame length less that pre - programmed minimum) transmit aborted (collision detected in the d - chann el) the CMX635 contains a fifo, for each of the b receive and transmit channels and the d receive and transmit channel (6 total). the fifos are implemented as part of a 1024 byte ram and the fifo depths can be independently configured for each channel, in 4 byte increments, up to the 1024 byte ram size. the sum of fifo sizes must not exceed the 1024 byte limit. a full set of fifo status indicators are available for each channel including ?full?, ?empty?, ?near full?, ?near empty?, ?over - write? and ?under - re ad?. the ?near full? and ?near empty? status indicate when the fifo is 8 bytes from being full and 8 bytes from being empty respectively. the ?full? and ?empty? status have programmable polarity to allow for alternative interrupt generation on ?not full? and ?not empty?. each fifo can be individually cleared which obviates the need to read the entire fifo if an error or abort is detected. when a valid frame is detected the receive fifos are always written with all data between opening and closing flags, irrespective of the address matching and crc checking selected. the CMX635 hdlc controllers have extensive functionality to allow transmission and reception of multiple frames of data without processor intervention, subject to the fifo depths set. two me thods are available for multiple frame transmission. the first method allows multiple frames of the same length to be transmitted by writing an octet count register with the frame length and a frame count register with the required number of frames. the d ata to be transmitted is then written contiguously to the fifo. when hdlc transmission is enabled, the octet counter (which can be read asynchronously by software) defines the fifo data frame boundaries and decrements as each octet is transmitted. after ea ch frame the frame counter is decremented to a minimum count of 1. after each frame has been isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 17 d/635/2 transmitted an interruptable ?frame complete? flag is raised and after all of the frames have been transmitted an interruptable ?all frames complete? flag is raise d. the second method allows for multiple frames of differing lengths to be transmitted. the number of octets in the following frame is written to the fifo prepending the frame data. this is repeated for each frame in the multiple frame. during transmissio n the octet count is read from the fifo and used as in method 1 above along with the pre - programmed frame count. after each frame the next octet count is loaded from the fifo until all frames have been transmitted. a received octet counter is available to facilitate multiple frame reception. when a frame has been successfully received the software is required to respond to a good packet interrupt by reading and storing the received octet counter value. this value can then be used for reconstructing the rec eived frame when the fifo is eventually read. as the counter is only modulo 256, a rollover indication is provided to enable handling of long frames. 1.5.3 t he iom interface the CMX635 contains an industry standard iom - 2 interface to facilitate data transfer a nd programming of other iom - 2 compliant devices such as the cmx625 isdn ta pots interface. a summary of the iom - 2 standard may be found in section 1.7.2 of this document. the interface operates in terminal mode where 3 channel s of 4 octets are transmitted per frame. the iom - 2 standard defines octets in each frame for: 8 bits of b1 and b2 data and 2 bits of d data. 8 bits of monitor 0 data + 2 handshake bits, used for layer - 1 device control functions. 8 bits of monitor 1 data + 2 handshake bits, used for programming and interrogation of other iom devices. 4 bits of control/indicate (ci) 0 data used for passing layer - 1 primitives. 6 bits of control/indicate (ci) 1 data used for real time status indication between iom devices. 2 8 - bit channels of inter - communication data (ic0 & ic1) used as alternative 64kb/s data channels. an 8 - bit tic (terminal ic) bus used for d - channel access from other layer - 2 devices. the iom interface can be configured as a timing master, where the iom clock (dcl) and the iom frame sync. (fsc) are generated by the device, or as a timing slave where an external device provides the clock and sync. signals. typically the CMX635 will be configured as a timing master when used in a te system and a timing slave (tak ing the clock and sync signals from a u interface transceiver) in an nt system. the CMX635 always operates as a control master device. the iom - 2 clock in terminal mode is nominally 1.536mhz giving 192 clocks per 8khz frame, or 2 clocks per data bit. the f sc and dcl are derived from the recovered 192khz s/t sample clock, which maintains pcm octet synchronisation. in nt mode, as a timing slave, the incoming fsc is used to synchronise the generated 192khz s/t data. the monitor channels (0 and 1) provide a me chanism for passing programming and information octets between the master and slave iom devices. only 1 channel can be active at a time, the active channel being selectable from the ?iom monitor channel control? register. the monitor handshake protocol in the iom specification is generated automatically within the CMX635 and any errors in the handshaking or received data will abort the transmit/receive sequence and raise interruptable abort flags in the ?iom status? register. the operation of the b, d and ic channels is fully autonomous and they are activated by routing data to and from the appropriate channels using the ?data routing? registers (section 1.5.6 ). data is transmitted in the selected monitor channel by writing to the ?monitor channel transmit? register when the tx channel is idle. the ?monitor tx buffer empty? status flag will indicate when isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 18 d/635/2 another transmit octet is required. the original data octet will be retransmitted continuously until the transmit buffer is r efreshed. setting the ?tx eof? bit in the ?monitor channel control? register when the ?tx buffer empty? status flag is asserted terminates the monitor frame. data is received in the selected monitor channel by reading from the ?monitor channel receive? re gister when the ?rx data available? flag is asserted. the ?rx eof? flag indicates the end of a received iom frame and the ?rx abort? flag indicates an error in reception. the command/indicate channels provide a mechanism for passing ?real time? layer - 1 pr imitives (ci0) and status flags (ci1) between iom devices. data written to the ?ci transmit? registers will be immediately reflected in the appropriate ci channel and will persist until the register data is changed. the received ci channel is read from the ?ci receive? registers and ?new ci data? flags indicate when two consecutive frames contain new and identical ci data. the ?ci0 transmit? register contains extra locations to enable an iom timing request (tim) to be generated and to control the bus activ ation request (bac) bit in the tic channel. the tim is used to request activation of the upstream iom device and pulls the du pin low from its deactivated open - drain state. when the CMX635 is configured as a timing master, the iom bus can be deactivated b y turning off the dcl and fsc and placing the iomtx pin in the open drain state. an iom deactivation sequence can be optionally invoked that ensures deactivation is not completed until 4 frames of the primitive dc (deactivate confirmation - 1111b) has been received in the ci0 channel from all downstream devices. the CMX635 implements a sub - set of the tic bus control functions. the tic bus allows layer - 1 control of the d - channel from other iom devices. the CMX635 enables control of the transmitted bac bit i n nt applications when required by the u transceiver device but does not generate or monitor tic bus addresses. in te mode the d - channel access function will automatically operate the stop/go (s/g) bit to prevent other layer - 1 devices from accessing the d - channel when occupied by the CMX635. the received bac bit is monitored to establish when other layer - 1 devices require access to the d - channel. the CMX635 can be configured to reverse its tx and rx pin directions in the ic channels and/or the mon1 and ci1 channels. this feature is known as ?bus reversal? and enables the CMX635, when configured as a downstream iom device, to communicate with other downstream iom devices. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 19 d/635/2 1.5.4 the g.711 codec and analogue gain path the pcm codec - filter performs voice digitisati on and reconstruction and incorporates encoder bandpass and decoder lowpass filters with pre and post - filtering and with selectable a - law and - law companding. in each case the coder and decoder process a companded 8 - bit pcm word following ccitt recommenda tion g.711 for a - law and - law conversion. the encoder bandpass filter and decoder lowpass filter provides passband flatness and stopband rejection according to ccitt recommendation g.712. the lowpass filter contains the required (sin x)/x compensation. f lexible receive and transmit digital gain control and analogue routing controls are provided to enable configuration into pots or isdn feature - phone applications. examples of the possible configurations for pots are: sine, square or trapezoid ring freque ncy routed to speaker output with programmable amplitude. cadence controlled within CMX635 or externally. received analogue codec signal routed to earpiece output (slic/hybrid input). call progress or dtmf tones summed with or replacing codec signal to ear piece at programmable amplitude. call waiting tone (sas), caller line id on call waiting alert signal (cas) and fsk caller id data replacing signal to earpiece at programmable amplitude. received dtmf tones from receive codec routed to dtmf decoder for rem ote signalling detection. dtmf tones from pots interface routed to dtmf decoder for dialled number detection. examples of the possible configurations for isdn phones are: input from 1 of 2 microphone inputs switchable through programmable gain to transmit codec. allows transducer matching and a.g.c. function for speakerphone operation. independent programmable microphone channel attenuation for speakerphone algorithms. received analogue codec signal routed to earpiece and/or loudspeaker output. loudspeaker amplifier has programmable gain for volume control and speakerphone attenuation. programmable proportion of microphone channel can be added to earpiece output as ?sidetone?. dtmf tones can be routed to earpiece/speaker for dialling feedback or to transmit codec for remote dtmf signalling. full range of pre - programmed tones can be routed to speaker at programmable amplitude for ringing. the programming guide, section 1.6 , details the full range of routing and gain control functio ns available. 1.5.5 the tone generator and tone decoder the tone generator can be used to generate tones for either dtmf tones, call progress tones, ringing signals for isdn phones and fsk data tones for pots caller id functions. the tones available are pre - p rogrammed and grouped into 4 tone fields of up to 256 tones each. to select a particular tone or tone pair the ?tone/codec control? register is first written with the required tone field and the ?tone? register is then written with the selection from that field. the tone enable register allows independent power save control for the various tone types. the ring signal can be configured as a sine, square or trapezoidal output at a number of frequencies between 17hz and 51hz. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 20 d/635/2 the fsk tones are automatically g enerated when the fsk function is enabled and fsk data is written to the transmit uart. the tone frequencies for fsk transmission can be selected to be compliant with either bell 202 or v.23 standards. the fsk uart can be programmed to convert the transmi t data from octets to serial asynchronous data characters by adding start and stop bits or to transmit the octets synchronously with no start or stop bits. the baud rate is fixed at 1200 baud. status flags indicate when the transmit buffer requires more da ta and whether the buffer data has underflowed (the uart has started a new fsk character before the buffer has been refreshed). the dtmf decoder can accept a wide range of signal input amplitudes and produces a 4 bit dtmf character code that can be read f rom the ?dtmf receive data? register. status flags indicate when a valid tone is being detected and when it ceases. a subscriber pulse metering (spm) tone is available at a separate pin and can be programmed to 12khz or 16khz. when turned on, the output r amps from zero to full amplitude in approximately 4ms and ramps down again when turned off. this output allows emulation of the exchange call charging information for pots style payphones. 1.5.6 the channel routing block the channel routing block enables the ac tive data channels (b1, b2, d, ic1, ic2) to be flexibly routed between the st interface, the iom interface, the hdlc controllers and the codec. the available routing resources allow implementation of a full suite of loopback paths in either the transparen t (the incoming data continues to be passed to the original destination as well as looping back) or the non - transparent (original source/destination for data is disabled) modes. for b data routing, 4 prioritised routing registers are available. each regis ter contains a required 4 - bit source and 4 - bit destination port code. if there are conflicts between routing register data sources, the highest priority register routing will be implemented and the lower priority routing will be used as a destination only. d - channel routing is contained within a single register, which is divided into high and low priority routing 4 - bit nibbles. within each nibble 2 - bit source and destination port codes can be programmed. the priority mechanism works in a similar fashion to the b data routing above. 1.5.7 speaker phone functions the CMX635 contains comprehensive hardware filters, voice - above - noise detectors and signal path attenuators to allow a sophisticated implementation of software controlled speakerphone algorithms. the data processing is carried out on the 8khz 8 - bit wide pcm data in both the receive and transmit paths. status bits are available to indicate the presence of voice above the background noise in both the receive and transmit channels and the amplitude of the det ected voice can be read by software. the software algorithm can then decide which is the dominant channel and distribute the loop gain between receive and transmit channels. the following data processing functions on both the receive and transmit digital data paths are provided. note that all data processing is done on companded data in both channels. full wave rectification conversion of input data noise filtering of converted data with long time constant (~ 10 s) speech filtering of converted data wi th fast attack time constant (~ 1 ms) and selectable slow decay time constant (128, 256, 500 ms). auto gated noise filter i.e. the statistics integration is suspended when speech is detected in the channel. interrupt control system based upon filter output comparators, which provides three interrupt sources for each channel. the interrupt sources are: - isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 21 d/635/2 1) speech filter output > noise filter output 2) speech filter output > noise filter output + programmable threshold 3) speech filer output > noise filt er output + programmable threshold +/ - hysteresis value. interrupt generation when a change in any of the above conditions takes place. the user can poll the indicator flag bits to determine the exact condition that exists within the channel. a hysteresi s register to prevent rapid and spurious interrupts when a slow noisy signal moves close to the integrated background level. 1.5.8 the processor interface, top level status and power control the processor interface will automatically configure itself to operate with either multiplexed or non - multiplexed address/data architectures and with generic motorola or intel control signals. the processor interface type is configured after power - up by making a dummy write to the CMX635, which will monitor activity on the bus control lines and decode the appropriate interface type. when the non - multiplexed interface is detected it is mapped as 2 addresses on the processor bus that are distinguishable by the state of the asel pin during the read/write cycle. the first addre ss (asel set to binary 1) is the ?indirect? address register for the following data access and must be written first. the second address (asel = binary 0) accesses the register defined by the indirect address. typically the single address pin (asel) will b e connected to the lsb of the processor address bus. the indirect address is persistent and, once written, can be used for further data accesses to the same address (i.e. block reads/writes to the fifo data registers). when the multiplexed interface is de tected the internal register address is automatically demultiplexed from the ad bus and thus only single read/write cycles are required. the top level status register accumulates interrupt requests from the lower level blocks (as shown in figure 5 ) and can be programmed to generate a selective device level interrupt request dependent on the state of the top level interrupt mask. each lower level status register can be programmed to generate the interrupt requests to the top lev el status register via their own status masks. the status register /interrupt structure is hierarchical at 3 levels. the top level status register accumulates the interrupt requests from a number of level - 2 status register s. some of the level - 2 status regis ter s accumulate interrupt requests from level - 3 status register s. to respond to an interrupt originating from a level - 3 status register , both the top level status and the level - 2 status register s must be read to determine the source of the interrupt. the power control function includes a clock control register, and 3 enable registers. the clock control register selects the master crystal frequency (12.288mhz or 15.36mhz), the signal routed to the clkout pin (clock in or 1.536mhz) and allows the master crys tal oscillator to be disabled for complete power down applications. a hardware reset must be issued to re - enable the oscillator. the clock enable register can disable the system clock to individual blocks when not required thus saving power. the tone and a udio enable registers allow selective control of the analogue functions, codec and tone generator/decoder, progressively reducing power consumption as un - used functions are disabled. a power control status register is available which indicates external ?w ake - up? events on the st and iom busses. any activity on the st bus will trigger an st wake - up interrupt (if the interrupt is enabled with the appropriate masks), while the iomrx pin (du in te applications) being pulled low will trigger an iom wake - up inte rrupt. these interrupts will be generated even if the iom and st master clocks have been disabled. the ?power control status? register also contains 2 flags, ?ci0 channel idle? and ?iom deactivated? that indicate when the iom bus can be safely deactivated . the ?ci0 channel idle? isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 22 d/635/2 status indicates that there has been 2 consecutive iom frames received with the bus access bit set inactive (binary 1). in this condition there is no activity or pending activity in the ci0 channel. the ?iom deactivated? flag is va lid when the iom deactivate sequence is in use. the flag is asserted when all downstream devices have signalled complete deactivation. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 23 d/635/2 1.6 programming guide. 1.6.1 interrupt structure the CMX635 interrupt structure is hierarchical in nature with the interrupts fro m the various functional blocks converging in a top level status register to create a single chip level interrupt. the majority of interrupts can be interrogated from the next level of block status register s and a few require access to a third level of st atus register s. each status register at each level can be individually masked on a bit by bit basis with its own mask register. each level of status register is persistent, i.e. the status flags are latched and can only be cleared by reading the appropriat e register. to prevent continuous interrupts from being generated the software interrupt handler should either read the interrupting status register or temporarily mask the appropriate bit. the top level (level 1) status register comprises level - 2 interru pt sources as follows. bit interrupt source section no. [0] hdlc d - channel status 1.6.2.8.2 [1] hdlc b1 - channel status 1.6.2.8.2 [2] hdlc b2 - channel status 1.6.2.8.2 [3] st interface status register 1.6.2. 1.4 [4] iom interface status register 1.6.2.10.5 [5] tone generator status register 1.6.2.14.5 [6] clock & power control status register 1.6.2.11.4 [7] speakerphone interrupt status 1.6.2.12.6 the hdlc d, b1, b2 status register s and the st interface status register each have a level - 3 interrupt source as detailed in the relevant sections. the interrupt structure is shown diagrammatically in figure 5 . note that the reset value of the top level status register is the fully masked condition. for valid interrupts to be generated the top level mask register must be initialised early in the initialisation sequence. top level status register addr = $e1 reset = $00 tople vel status mask register addr = $e0 reset = $00 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 24 d/635/2 figure 5. interrupt structure top level status hdlc d status d rx fifo status level 3 rx status d tx fifo status 5 7 6 hdlc b1 status b1 rx fifo status level 3 rx status b1 tx fifo status 5 7 6 hdlc b2 status b2 rx fifo status level 3 rx status b2 tx fifo status 5 7 6 st status st state register multi - frame status 6 7 st interrupt iom status speaker phone status tone generat or status clock/ power status 0 1 2 3 4 5 6 7 level - 1 level - 3 level - 2 note : each status register has an associated mask register isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 25 d/635/2 1.6.2 CMX635 register definition and description the control registers of the CMX635 fall into the following broad categories: st interface block data routing block hdlc fifo control hdlc b1 - channel control hdlc b2 - channel control hdlc d - channel control iom interface control clock and power control speaker phone statistics audio/tone block top level status register these registers relate to t he main functional blocks as defined in the functional block diagram. note that the clock for each block being written or read must be activated using the clock enable register as detailed in section 1.6.2.11.1 1.6.2.1 st interface b lock the st interface block registers provide the necessary primitive control for activating and reporting the status of the st bus. they also provide the means to configure the CMX635 into its various operating modes and to control the multiframing capabi lities. the registers available in this block are: st control register st set - up register st interrupt register st status register interrupt mask register st state machine register st state machine mask register multiframe s register multiframe q register multiframe status/control register multiframe status mask register multiframe s bit counter isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 26 d/635/2 1.6.2.1.1 st control register addr = $80 reset = $00 (write/read) the following table lists the bit functions of the st control register. bit function [0] activate requ est (ph - ar) [1] deactivate request (mph - dr) [2] power up [3] unused [4] data request (ph - data) [5] priority (ph - data request parameter) [6] force echo 0 [7] unused unused bits in the control register will read back as binary 0. the activate reque st bit equates to the ph - ar primitive and initiates st bus activation when the CMX635 is configured in te mode. this bit is a transient signal that advances the st activation state machine to f4 when written with a binary 1 and reads back as binary 0. the deactivate request bit equates to the mph - dr primitive. it is a transient signal that returns the st activation state machine to f3 when written with a binary 1 and reads back as binary 0. this control is provided to allow implementation of timer t3 in s oftware. the power up bit advances the st activation state machine to f2 when written with a binary 1 and returns it to f1 when written with a binary 0. the status of the external power supply is expected to be indicated to the controlling processor by an external power supply monitor device. the data request bit equates to the ph - data request primitive and is used in conjunction with the priority bit to initiate the d - channel access procedure. the access procedure is initiated when written with a binary 1 and will be maintained until the required d - channel hdlc frame(s) has been transmitted. multiple hdlc frame transmission is possible if the d - channel frame count is set to > 1 and the required data is written to the fifos (see section 1.6.2.3 ). the current status of the data request bit can be read at any time. note that for a successful d - channel frame transmission the hdlc d - channel must be correctly initialised and enabled and data routing must be establishe d between the hdlc block and the st interface. the priority bit sets the primary priority level required for a pending d - channel access. a priority of binary 0 will require 8/9 d - channel echo bits at binary 1 before access is allowed. a priority of binary 1 will require 10/11 echo bits at binary 1 before access is allowed. the secondary priority (i.e. 9 instead of 8 and 11 instead of 10) is automatically selected each time a successful access is made in accordance with itu - t i.430. the force echo0 bit may be used in nt mode to force the echo bits transmitted downstream to binary 0. this may be required in certain loopback configurations to prevent partial d - channel access by downstream devices. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 27 d/635/2 1.6.2.1.2 st set - up register addr = $82 reset = $01 (write/read) cur rently only bit 0 is utilised in the setup register. bit 0 is designated ?te mode?. a binary 1 written to this bit will configure the CMX635 as a te device. a binary 0 will configure the CMX635 as an nt device. when configured as a te device the in - buil t itu - t i.430 te activation state machine will be utilised, the reference clock timing is taken from the incoming st bit rate, the nt - te frame structure will be recognised and te multi - framing functionality will be invoked. when configured as an nt device the activation states are under software control, the reference clock timing is taken from the iom interface, the te - nt generated/ recognised and nt multi - framing functionality will be invoked. bits 1 - 7 will read back as binary 0. 1.6.2.1.3 st interrupt register / interrupt mask register addr = $85 reset = $00 (read only) - interrupt addr = $84 reset = $00 (write/read) - mask the st interrupt register and its associated mask register form part of the hierarchical interrupt structure (see section 1.6.1 ) and provides a level - 2 interrupt source to the top level status register. it represents an edge sensitive version of the associated st status register. bits 0 - 3 of the interrupt register are set to binary 1 whenever the corresponding status register bits change (0 to 1 or 1 to 0). bits 4 - 7 are set to binary 1 only when the corresponding status bits change from binary 0 to binary 1. all bits are reset to binary 0 when the interrupt register is read by software. the ma sk register will prevent the corresponding bit of the interrupt register from generating an st block interrupt when set to binary 0. 1.6.2.1.4 st status register addr = $83 reset = $00 (read only) the st status register indicates the status of the st interface acc ording to the definitions in the following table. bit function [0] connect indication (mph - ii(c)) [1] activate indication (ph - ai) [2] activate error (mph - ei1) [3] data indication (ph - data ind) [4] collision [5] unused [6] multi - frame interrupt [7] state machine interrupt these status bits represent a real time indication of st interface status. the edge - detected version is available in the st interrupt register, which is used along with the mask register to generate st status interrupts. the con nect indication bit will be set to binary 1 when the device is connected, i.e. state f3 and above. it will be reset to binary 0 when the device is in state f1 or f2. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 28 d/635/2 the activate indication bit will be set to binary 1 when the device is activated i.e. wh en in state f7 or f8. the data indication bit will be set to binary 1 when a pending d - channel access request has been granted and will be reset to binary 0 on completion of the frame. the collision bit will be set to binary 1 when a collision is detecte d during the d - channel access procedure. it is provided for monitoring purposes only. the multi - frame interrupt bit indicates a change in status of the multi - frame block, which represents a level - 3 interrupt source. the state machine interrupt block ind icates a change in status of the state machine register, which represents a level - 3 interrupt source. 1.6.2.1.5 st state machine register/ state machine mask register state machine addr = $87 reset = $00 mask reset addr = $88 reset = $00 (write/read) the st st ate machine register forms a level - 3 interrupt source (see section 1.6.1 ) for the level - 2 st status register (section 1.6.2.1.4 ). the st state machine register provi des visibility of the state of the activate/deactivate state machine in the st interface and the ability to write the required state for nt mode operation. it also provides an indication of the detected info signals. the register bits are defined in the following table. bit function [0] state variable [0] [1] state variable [1] [2] state variable [2] [3] synced [4] info0 detected [5] info1 detected [6] info2 detected [7] info3 or 4 detected the 3 bit state variable register can be configured to interrupt at each change of state via the sm mask register. in te mode the activation/deactivation control is automatic (with the exception of expiry of t3) whilst in nt mode state transition is controlled in software by writing the appropriate code to the state variable bits. the state decoding is as follows. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 29 d/635/2 encoding nt state te state 000b g1 f1 001b g2 f2 010b g3 f3 011b g4 f4 100b unused, set to 0 f5 101b unused, set to 0 f6 110b unused, set to 0 f7 111b unused, set to 0 f8 the synced b it will be set to binary 1 when the st interface has achieved frame synchronisation. the info0/1/2 bits will be set to binary 1 when the appropriate info signal has been detected. the info3 or 4 bit will be set to binary 1 when info3 is detected in nt mo de and info4 is detected in te mode. the sm mask register will allow any change of state of the state machine register to generate an interrupt when the equivalent bit in the mask register is set to binary 1. 1.6.2.1.6 multi - frame s register addr = $89 reset = $00 (write/read) all 5 defined channels of s data can be generated/received by the CMX635. the s register represents a single bit from each channel and must be written every 5 st frames in nt mode and read every 5 frames in te mode. there will therefore be 4 write/reads required in 1 multi - frame (5ms) to build up the 5 channels of 4 bit s data. the mf status register (see section 1.6.2.1.8 ) indicates the start of a multi - frame and thus when the data for bit[0] of each s channel must be written/read. it also indicates when new s data is required or available and a number of other status flags. the register bits are defined as follows. bit function [0] sc1x [1] sc2x [2] sc3x [3] sc4x [4] sc5x [5] unused [6] unused [7] unused isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 30 d/635/2 1.6.2.1.7 multi - frame q register addr = $8a reset = $0f (write/read) the multi - frame q register represents the complete 4 bits of the q channel and is written every 20 st frames in te mode and read every 20 frames in nt mode. the mf status reg ister (see section 1.6.2.1.8 ) indicates when new q data is required or available. the q register bits are allocated as follows bit function [0] (lsb) q1 [1] q2 [2] q3 [3] q4 [4] unused [5] unused [6] unu sed [7] (msb) unused 1.6.2.1.8 multi - frame status register/ mask register addr = $8b reset = $00 (read/write) status addr = $8c reset = $00 (write/read) mask the multi - frame status register forms a level - 3 interrupt source (see section 1.6.1 ) for the level - 2 st status register (section 1.6.2.1.4 ). the status bits are defined in the following table. bit function [0] (lsb) tx data under - run read only [1] rx data over - run r ead only [2] tx buffer empty read only [3] rx buffer full read only [4] start of multi - frame read only [5] multi - frame synced read only [6] unused [7] (msb) multi - frame enable read/write note: tx data and tx buffer refer to the q data and registe r in te mode and the s data and register in nt mode. rx data and rx buffer refer to the s data and register in te mode and the q data and register in nt mode. the status bits are cleared by reading from the status register and, in the case of rx buffer full and tx buffer empty, by reading or writing the appropriate rx/tx register. the least significant 6 bits of the multi - frame status register are read only status bits. the most significant bit ? multi - frame enable ? is can be written and when set to a binary 1 will enable multi - frame operation. the tx data under - run bit will be set to binary 1 if the tx buffer has not been refreshed with data before new frame data is required. the rx data over - run bit will be set to binary 1 if new data is received be fore the previous data has been read from the receive buffer. the receive buffer will be overwritten with the new data. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 31 d/635/2 the tx buffer empty bit will be set to binary 1 when the data from the tx buffer has been transferred to the multi - frame transmitter. this bit indicates the earliest that new tx data can be loaded into the tx buffer. in nt mode, new data must be loaded before the tx data under - run indication (approx. 5 st frames or 625 m s from tx buffer empty) or the s bit data sequence will be corrupted . in te mode the tx under - run indication will occur approx. 20 st frames (2.5 ms) after the tx buffer empty indication and the q register will be retransmitted if the q register is not updated. the rx buffer full bit will be set to binary 1 when new rx da ta is available for reading. the rx buffer must be read before the rx over - run indication or rx data could be lost. this will occur approx. 5 st frames (625 m s) after rx buffer full in te mode and 20 st frames (2.5ms) in nt mode. the start of multi - frame bit will be set to binary 1 at the earliest point that bit 1 of the 5 s data channels can be written to the s register in nt mode. the multi - frame synced bit is set to binary 1 when the correct sequence of fa and m bits have been detected, indicating that the multi - frame is synchronised. 1.6.2.1.9 multi - frame s bit counter addr = $8d reset = $00 (read only) the s bit counter indicates which of the 4 bits of the 5 sc registers is currently being received in te mode. the counter will start at decimal 0 at the beginn ing of a multi - frame and count up 1 every 5 st frames to a maximum of decimal 3. the counter aids reconstruction of the 5 sc registers. the following table defines the bits. bit function [1:0] binary encoded s bit count [7:2] unused, reads back as bin ary 0 1.6.2.2 data routing block the data routing block controls the source and destination ports for the b1, b2 and d - channel data. the available ports for b - channel data are: st b1 - channel st b2 - channel hdlc b1 - channel hdlc b2 - channel iom b1 - channel iom b2 - ch annel iom ic1 channel iom ic2 channel codec isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 32 d/635/2 the available ports for d - channel data are: st d - channel hdlc d - channel iom d - channel the b and d - channel routing is controlled by a prioritised set of 5 routing registers as follows: b route control 1 (highest priority) addr = $b0 reset = $00 b route control 2 addr = $b1 reset = $00 b route control 3 addr = $b2 reset = $00 b route control 4 (lowest priority) addr = $b3 reset = $00 d route control addr = $b4 reset = $00 the 4 b and 1 d registers can all written and read. the bit definition for all 4 b routing registers is identical and is shown in the following table. bit function [3:0] source/destination code a [7:4] source/destination code b each b - channel source/destination port is allocated a 4 - bit code and the b - channel data is routed between code a and code b ports. each route control register can have an independent pair of ports specified, but where a conflict arises with a higher priority register the lower priority port can only receive da ta. specifying the same code for a and b within a single routing register will set up a loop - back. the b - channel port codes are as follows: code (hex) port 0 off - no routing connection 1 st b1 - channel 2 st b2 - channel 3 iom b1 - channel 4 iom b2 - chann el 5 iom ic1 channel 6 iom ic2 channel 7 hdlc b1 - channel 8 hdlc b2 - channel 9 codec a to f unused ? selects no routing example 1: route st b1 to hdlc b2, st b2 to codec. b route control 1 = 18h b route control 2 = 29h b route control 3 = 00h b ro ute control 4 = 00h isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 33 d/635/2 example 2: route st b1 to st b1, st b2 to st b2, st b1 to codec, st b2 to iom ic1 b route control 1 = 11h b route control 2 = 22h b route control 3 = 19h b route control 4 = 25h in this case a loopback has been implemented in both b - channels, whilst the downstream data is being passed through to the codec and iom ic1 channels. data generated by the codec and iom bus is lost. the bit definition for the d routing register is shown in the following table. bit function [1:0] source/ destination code b (low priority) [3:2] source/destination code a (low priority) [5:4] source/destination code b (high priority) [7:6] source/destination code a (high priority) the operation of the d routing register is similar to the b routing regist ers but the routing priority is defined in 2 halves of a single register. the source/destination codes are 2 bits wide as follows: code (bin) port 00 off - no routing connection 01 st d - channel 10 hdlc d - channel 11 iom d - channel example 3: loop bac k st d - channel while passing d - channel through to iom d - channel. d route control = 01010110b 1.6.2.3 hdlc fifo control the CMX635 hdlc fifos are constructed from a single 1024 x 8 ram, which can be flexibly subdivided into the 6 required channels (b1 rx and t x, b2 rx and tx, d rx and tx) under software control. each fifo has its own status register and associated mask register to enable efficient block transfer between CMX635 and processor. the fifo registers available are: 6 base address registers, one for each channel, defining the ram base address for each fifo. 3 read ports for the rx fifos and 3 write ports for the tx fifos. a fifo clear register for resetting each fifo individually. 6 status and 6 associated mask registers, 1 of each for each channel. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 34 d/635/2 1.6.2.3.1 base address registers the 6 base address registers used to partition the internal ram into the 6 required fifos are: d tx base address addr = $60 reset = $00 (write/read) d rx base address addr = $61 reset = $10 (write/read) b1 tx base address addr = $62 reset = $20 (write/read) b1 rx base address addr = $63 reset = $58 (write/read) b2 tx base address addr = $64 reset = $90 (write/read) b2 rx base address addr = $65 reset = $c8 (write/read) the order of partitioning of the ram is always as shown above with the d tx fifo being nearest the bottom (address 0) and the b2 rx fifo nearest the top. the base addresses can be set on 4 byte boundaries and are derived internally as a concatenation of the base address register (as the most significant 8 bits of the address) and binary 00 (as the least significant 2 bits). the base address of the next highest fifo must always be greater than that of the previous fifo base address. the reset values of the fifo base address registers give fifo depths of 64 bytes for the d rx and tx channels, 224 bytes for the b1/b2 rx and tx channels. 1.6.2.3.2 read/write ports the data for hdlc transmission/reception is written/read from these ports as raw unencoded octets (if autonomous mode of operation is selected). the appropriate tx enable must be asserted before the transmit fifos can be written to. the 6 fifo ports are: d tx channel addr = $68 (write) d rx channel addr = $6b (read) b1tx channel addr = $69 (write) b1 rx channel addr = $6c (read) b2tx channel addr = $6a (write ) b2 rx channel addr = $6d (read) 1.6.2.3.3 fifo clear register addr = $6e (write) each fifo channel can be individually cleared by writing a binary 1 to the appropriate bit position. the data is not actually written, but is used to generate a transient clear st robe. the read and write pointers will be set equal to each other and the base address. this gives a convenient method to re - initialise the fifo if required. the bit definition is shown in the following table. bit function [0] d - channel tx fifo clear [1] d - channel rx fifo clear [2] b1 - channel tx fifo clear [3] b1 - channel rx fifo clear [4] b2 - channel tx fifo clear [5] b2 - channel rx fifo clear [6] unused [7] unused isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 35 d/635/2 1.6.2.3.4 status and mask registers each fifo channel has an associated status (read) and mask (write/read) register as follows: d tx status addr = $70 reset = $00 d tx mask register addr = $72 reset = $00 d rx status addr = $71 reset = $00 d rx mask register addr = $73 reset = $00 b1 tx status addr = $74 reset = $00 b1 tx mask regist er addr = $76 reset = $00 b1 rx status addr = $75 reset = $00 b1 rx mask register addr = $77 reset = $00 b2 tx status addr = $78 reset = $00 b2 tx mask register addr = $7a reset = $00 b2 rx status addr = $79 reset = $00 b2 rx mask register addr = $7b reset = $00 these registers form a level - 3 interrupt source to the level - 2 hdlc b1, b2 and d hdlc status registers (section 1.6.2.8.2 ). the status registers all have the same bit allocations as shown in the following tab le. bit function [0] fifo over write - clears on stats reg read [1] fifo under read - clears on stats reg read [2] fifo empty flag - clears on fifo status change [3] fifo full flag - clears on fifo status change [4] fifo near empty (tx fifo o nly) - clears on fifo status change [5] fifo near full (rx fifo only) - clears on fifo status change [6] unused [7] unused the fifo overwrite bit is set to binary 1 if a write to the fifo is made when full. a write to the fifo can be via the data po rt for a tx fifo or an internal write for an rx fifo . the fifo under - read bit is set to binary 1 if a read from the fifo is made when empty. a read from the fifo can be via the data port for an rx fifo or an internal read for a tx fifo . the fifo empty bi t has a programmable polarity. when the mask register bit 6 is binary 0, the empty flag will be set to binary 1 when the last available location in the ram is read. it will only clear to binary 0 when the fifo is written. when the mask register bit 6 is bi nary 1 the sense of the flag is reversed - i.e. it becomes fifo not - empty. the fifo full bit has a programmable polarity. when the mask register bit 7 is binary 0, the fifo full bit will be set to binary 1 when the last remaining location in the ram is written. it will only clear to binary 0 when the fifo is read. when the mask register bit 7 is binary 1 the sense of the flag is reversed ? i.e. it becomes fifo not - full. the fifo near empty bit is only applicable to the tx fifo s and will be set to binary 1 when only 8 octets remain in the fifo . it will only clear to binary 0 when the fifo contains more than 8 octets of data. for the rx fifo s this bit is permanently set to binary 0. the fifo near full bit is only applicable to the rx fifo s and will be set to binary 1 when only the fifo is 8 octets short of being full. it will only clear to binary 0 when the fifo is read and more isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 36 d/635/2 than 8 octets of space is available in the fifo . for the tx fifo s this bit is permanently set to binary 0. the mask register bit s 0 to 5, when set to binary 0, will prevent a binary 1 in the corresponding status register bit position from generating a level - 3 interrupt request (see section 1.6.1 ) to the level - 2 hdlc status register (see 1.6.2.8.2 ). the function of mask bits 6 and 7 is as previously explained. 1.6.2.4 hdlc rx channel control each of the 3 rx channels (b1, b2 and d) has a similar set of control registers as follows. rx mode register 9 address matching control registers level - 2 hdlc status register and mask register level - 3 rx status register and mask register rx octet counter rx mode register d - channel addr = $00 reset = $00 (write/read) b1 - channel addr = $20 reset = $00 (write/read) b2 - channel addr = $40 reset = $00 (write/read) the rx mode register controls the receive channel operation as follows: 1.6.2.5 d channel rx mode register bit 1.6.2.6 function [2:0] minimum expected receive octet count [3] receive enable [4] reserved [5] unused [6 ] unused [7] unused 1.6.2.7 b channel rx mode register bit 1.6.2.8 function [2:0] minimum expected receive octet count [3] receive enable [4] receive channel transparent mode [5] reserved [6] unused [7] unused the minimum receive octet count (all received octe ts between opening and closing flags) sets the limit below which an error status is generated for short received frames. the receive enable bit when set to binary 1 is the master enable for the rx channel and must be enabled to read the fifo. when disable d, any data remaining in the fifo will be lost and the fifo reset. the receive channel transparent mode bit when set to binary 1 enables the transparent receive mode in the b - channels which does not process flags, bit stuffing, addresses or crc. all recei ved isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 37 d/635/2 data is written to the fifo and the processing of framing and protocols becomes the responsibility of the controlling software. 1.6.2.8.1 address matching control registers the user can initialise up to 4 1 st (a1 - a4) and 4 2 nd (b1 - b4) address - matching register s for comparing incoming sapi and tei address fields. the combination of matching performed with these registers is set by the match request register. only the most significant 7 bits are compared as the lsb of each address field acts as an address extens ion bit and does not form part of the address. the registers can all be read or written to. the address matching registers are designated as follow: address match register a1, a2, a3 and a4 (reset = $00): a1 d - channel addr = $01 a1 b1 - channel addr = $ 21 a1 b2 - channel addr = $41 a2 d - channel addr = $02 a2 b1 - channel addr = $22 a2 b2 - channel addr = $42 a3 d - channel addr = $03 a3 b1 - channel addr = $23 a3 b2 - channel addr = $43 a4 d - channel addr = $04 a4 b1 - channel addr = $24 a4 b2 - channel addr = $44 address match register b1, b2, b3 and b4 (reset = $00): b1 d - channel addr = $05 b1 b1 - channel addr = $25 b1 b2 - channel addr = $45 b2 d - channel addr = $06 b2 b1 - channel addr = $26 b2 b2 - channel addr = $46 b3 d - channel addr = $07 b3 b1 - chan nel addr = $27 b3 b2 - channel addr = $47 b4 d - channel addr = $08 b4 b1 - channel addr = $28 b4 b2 - channel addr = $48 match request register (reset = $00) d - channel addr = $09 b1 - channel addr = $29 b2 - channel addr = $49 the match request register for each channel defines the extent of address matching according to the table below: bit function [0] match 1 st address byte to selected a match registers [1] match 2 st address byte to selected b match registers [2] match broadcast addresses, 1 st add ress to ffh, 2 nd address to feh [3] use match registers a1 and/or b1 [4] use match registers a2 and/or b2 [5] use match registers a3 and/or b3 [6] use match registers a4 and/or b4 [7] unused bit 0, when set to binary 1, enables address matching on t he 1 st received address octet and can be used in isolation for single address octet hdlc frames. bit 1, when set to binary 1, enables address matching on the 2 nd received address octet and must be used in conjunction with bit 0 set to binary 1. if both b it 0 and bit 1 are set to binary 0, address matching is turned off and all addresses will ?match? i.e. all received frames will be written to the fifo and can generate receive interrupts. bits 3 to 6 define how many and which addresses are compared to the incoming address fields. a binary 1 will enable the relevant match register, which will be compared, along with other selected match registers, against the incoming address fields. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 38 d/635/2 1.6.2.8.2 level - 2 hdlc status and mask registers the layer - 2 hdlc status register (read only) indicates the status of the receive and transmit channels and accepts level - 3 interrupt requests from the rx and tx fifo s. there is a status register and a mask register (write/read) for each channel as follows: status registers: d - channel a ddr = $0b reset = $00 b1 - channel addr = $2b reset = $00 b2 - channel addr = $4b reset = $00 mask registers: d - channel addr = $0d reset = $00 b1 - channel addr = $2d reset = $00 b2 - channel addr = $4d reset = $00 the bit definition is as follows: bi t function [0] (lsb) received good frame [1] address match [2] tx abort [3] tx frame completed [4] tx all frames completed [5] layer - 3 status register interrupt [6] rx fifo status interrupt [7] (msb) tx fifo status interrupt the received good fra me bit is set to binary 1 when all of the conditions for a successful frame reception have been met (above minimum length, address matched, aligned flags, correct crc). the address match bit is set to binary 1 when a successful match has been found with t he specified addresses (see section 1.6.2.8.1 ). note that if both 1 st and 2 nd address matching is specified, the status will not change until the 2 nd address field successfully matches. the tx abort bit is set to binary 1 if the transmission is aborted. this can occur if the tx fifo runs out of data (fifo empty) or in the d - channel, if the d - channel access is removed possibly due to a detected collision. the tx frame completed bit is set to binary 1 when a fram e has been successfully transmitted. the tx all frames completed bit is set to binary 1 when all frames in a multi - frame hdlc transmission have been completed. bits 5, 6 and 7 indicate an interrupt request from level - 3 status registers. the mask registe r bits, when set to binary 0, will prevent a binary 1 in the corresponding status register bit position from generating a level - 2 interrupt request (see section 1.6.1 ) to the level - 1 top level status register. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 39 d/635/2 1.6.2.8.3 level - 3 receive status and mask registers there is a level - 3 status register (read only) and a mask register (read/write) for each channel as follows: status registers: d - channel addr = $0c reset = $00 b1 - channel addr = $2c reset = $00 b2 - channel ad dr = $4c reset = $00 mask registers: d - channel addr = $0e reset = $00 b1 - channel addr = $2e reset = $00 b2 - channel addr = $4e reset = $00 the level - 3 receive status register provides further information on aborted receive frames as follows: bit fu nction [0] crc error [1] rx octet mis - aligned error [2] rx packet aborted [3] rx short packet [4] rx octet counter roll over [5] unused [6] unused [7] unused an rx octet mis - aligned flag is generated when a non - integer number of octets have been received between an opening and closing flag. an rx packet aborted flag is generated when 7 consecutive binary 1s are received during a frame. an rx short packet flag is generated when the received packet length is less than the pre - programmed minimum. the rx octet counter roll over bit is set to binary 1 when the rx octet counter rolls over (see section 1.6.2.8.4 ). the mask register bits, when set to binary 0, will prevent a binary 1 in the corresponding s tatus register bit position from generating a level - 3 interrupt request (see section 1.6.1 ) to the level - 2 hdlc status register. 1.6.2.8.4 rx octet counter d - channel addr = $0f reset = $00 (read only) b1 - channel addr = $2f r eset = $00 (read only) b2 - channel addr = $4f reset = $00 (read only) the rx octet counter counts the number of octets received into the rx fifo - note modulus of 256 means that rollover could occur on large fifos. level - 3 receive status register bit 5 war ns of this condition (see section 1.6.2.8.3 ). isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 40 d/635/2 note: when flags are used as the receive interframe idle mode (flag idle) the rx octet counter must be read within 900us (d channel), or 250us (b channel), of recei pt of a received good frame interrupt for reliable operation. 1.6.2.9 hdlc tx channel control each of the 3 tx channels (b1, b2 and d) has a similar set of control registers as follows. tx mode register 2 tx address registers tx frame count register tx octet cou nt register 1.6.2.9.1 tx mode register d - channel addr = $10 reset = $00 (write/read) b1 - channel addr = $30 reset = $00 (write/read) b2 - channel addr = $50 reset = $00 (write/read) the tx mode register controls the hdlc transmit functions. the bit definition is given in the following table: bit function [0] link list mode [1] user crc mode [2] transparent mode [3] tx enable [4] single address mode [5] user address mode [6] force error [7] back to back mode a binary 1 in the appropriate bit position selects the described function. link list mode is a mode of operation intended for multi - frame hdlc transmissions. it enables the fifo s to autonomously transmit multiple frames of varying lengths and is used in conjunction with the tx frame count registe r (see 1.6.2.9.3 ). to use link list mode, the fifo s are written with multiple frames of data, the first octet of which is the number of data octets in the following frame. during transmission at the start of eac h new frame the octet count is automatically read from the fifo and loaded into the tx octet counter (section 0 ). this process is repeated for the number iterations specified in the tx frame count registe r. user crc mode when selected requires the crc octets to be written to the tx fifo and included in the tx octet count. the software must calculate the correct crc value. when this mode is not selected the crc values are automatically calculated and appen ded to the frame and are not included in the octet count. transparent mode when selected will cause only the fifo data to be transmitted with no hdlc formatting at all (i.e. no flags, bit stuffing, address octets or crc octets). tx enable is the master e nable for the tx channel. this bit must be set to binary 1 before the relevant fifo can be written. in addition any data remaining in the fifo when this bit is set to binary 0 will be lost i.e. the fifo will be reset. single address mode when selected, c auses only a single address octet to be prepended to the data octets (tx address high register and only if user address mode is not selected). isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 41 d/635/2 user address mode when selected will prevent either tx address high or tx address low from being prepended to th e data octets. the required address octet(s) must be written to the fifo along with the data octets. force error when selected will cause an erroneous crc value to be generated. this is used for system test purposes only. back to back mode when selected will cause a single flag to be generated between consecutive frames of a multi - frame transmission i.e. a shared start/end flag. 1.6.2.9.2 tx address registers 2 tx address registers for each channel define the address to be transmitted in the first and second oct et of a frame when the user address mode is not selected. the registers are: tx address high (1 st octet address): d - channel addr = $15 reset = $00 (write/read) b1 - channel addr = $35 reset = $00 (write/read) b2 - channel addr = $55 reset = $00 (write/ read) tx address low (2 nd octet address): d - channel addr = $14 reset = $00 (write/read) b1 - channel addr = $34 reset = $00 (write/read) b2 - channel addr = $54 reset = $00 (write/read) 1.6.2.9.3 tx frame count register d - channel addr = $16 reset = $00 (write /read) b1 - channel addr = $36 reset = $00 (write/read) b2 - channel addr = $56 reset = $00 (write/read) the tx frame count register sets the required number of frames to be transmitted in a multi - frame transmission and, in the b channel, allows an inter frame fill of hdlc flags (flag idle). the bit definition for b channel operation is given in the following table: bit function [6:0] transmit frame count [7] set flag idle mode bits [6:0] ([7:0] in the d channel) allow a maximum frame count of 127 (2 55 for d channel) to be set for multi - frame transmissions. as the end of each frame is transmitted, the register value is decremented. this allows multiframe transmission progress to be monitored. the hdlc channel returns to idle mode when the counter rea ches zero. the count should be set to 1 for single frame transmissions. note: setting the frame count to a non - zero value is the ?normal? method of initiating a transmission in the b channels, however transmission will not begin until valid routing has bee n set up. transmission in the d channel also requires the st interface data request primitive to be written. bit [7] in the b channel, when set to binary 1, enables flag idle mode of transmission whereby interframe time is filled with continuous hdlc flag s. delays between frames may occur in single frame transmission mode, when the frame counter decrements to zero or when the fifo becomes empty in multiframe transmission mode. if bit [7] is set to binary 0, mark idle mode is selected whereby interframe fil l is hdlc marks (binary 1, no signal). isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 42 d/635/2 tx octet count register d - channel addr = $17 reset = $00 (write/read) b1 - channel addr = $37 reset = $00 (write/read) b2 - channel addr = $57 reset = $00 (write/read) the tx octet count register sets the number of octets to be transmitted in any frame. this must be set for single frames and non - linked list mode of multi - frame transmission in which the frame lengths must be constant. the maximum frame length for multi - frame operation is 256 fifo octets. to transmi t single frames greater than 256 octets, the tx octet counter must be re - written before it decrements to 0. for non - linked list multi - frames the tx octet count is used to delimit the fifo data into individual constant length frames. in linked list mode m ulti - frames the octet count is written to the fifo as the first octet of each frame and is automatically loaded into the octet count register to establish the length of the current frame. the frame length can therefore be variable. 1.6.2.10 iom interface control the iom interface allows export and import of b and d - channel data as well as programming control of other iom compliant devices such as the cmx625 pots codec. the registers available to control the interface are: iom control register monitor channel co ntrol register monitor channel tx register monitor channel rx register iom status register, mask register and real time status ci0 and ci1 channel transmit and receive registers 1.6.2.10.1 iom control register addr = $90 reset = $00 (write/read) the iom control register provides the control of the iom operating modes. the bits are defined according to the following table: bit function [0] timing master [1] ic channel bus reversal [2] reserved ? set to binary 0 [3] iom enable [4] use deactivate state machi ne [5] active outputs [6] monitor channel bus reversal [7] unused the timing master bit when set to binary 1 will set the CMX635 as the iom timing master. in this mode the iom frame sync (fsc) and clock (dcl) are generated by and exported from the cmx 635. when set to binary 0 these signals are imported from an external timing master device isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 43 d/635/2 (i.e. when configured into an nt system). the CMX635 will always operate as the iom control master. the ic channel bus reversal bit when set to binary 1 enables bus reversal in the ic1 and ic2, channels. similarly, the monitor channel bus reversal bit when set to binary 1 enables bus reversal in the monitor1 and ci1 channels. this means that data is transmitted on the iom rx pins and received on the tx pins (c.f. nor mal operation - transmit on tx, receive on rx). note that the tx pin is designated dd when the CMX635 is an upstream device to other iom devices (te) and du when configured as a downstream device (nt). similarly the rx pin is du for a te and dd for an nt. a possible application of this function is when the CMX635 is configured in an intelligent nt system, where it is the downstream device to a u interface transceiver. to expand the pots capability to 2 ports, a cmx625 could be added as another downstream de vice. the rx and tx pins of the CMX635 and cmx625 would be connected together and bus reversal in the monitor channel would be selected to allow the cmx625 to be programmed from the CMX635 whilst still being capable of receiving b - channel data directly fro m the u interface. the use deactivate state machine bit when set to binary 1 will delay iom deactivation after a deactivate command has been issued, until 4 frames of the primitive dc (deactivate confirmation - 1111b) has been received from all downstrea m devices. the active outputs bit when set to binary 1 will cause the tx pin to change from an open drain output, requiring an external pull - up resistor, to a fully driven output. this mode enables lower power and faster drive of the dd line in te mode as an external pull - up resistor is not required. to avoid contention on the dd line, active output mode should not be selected when bus reversal mode is also selected. 1.6.2.10.2 monitor channel control register addr = $92 reset = $02 (write/read) the monitor channel control register selects the active monitor channel and provides for control of the monitor channel transmit sequence. the bits are defined according to the following table: bit function [0] transmit eof code [1] monitor channel #1 select [2] tx abor t request [7:3] unused the transmit eof bit must be set to binary 1 when all of the required data octets have been transmitted. this causes an eof code to be transmitted (mx high for 2 consecutive frames). the monitor channel select bit should be set to binary 1 to select transmission (and reception) in the mon1 channel. set to binary 0 to select mon0 as the active channel. the tx abort bit when set to binary 1 will cause an abort code to be transmitted (mx high for 2 consecutive frames) and return t he iom monitor channel interface to the idle state. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 44 d/635/2 1.6.2.10.3 monitor channel tx register addr = $91 reset = $ff (write only) this register should be written with the desired monitor channel transmit data when the tx buffer empty bit in the status register is se t to binary 1 (see section 1.6.2.10.5 ). note that there is no maximum response time requirement to the tx buffer empty flag as the transmission speed is controlled by a hardware handshake mechanism (section 1.7.2 ). 1.6.2.10.4 monitor channel rx register addr = $93 (read only) this register contains the latest monitor channel receive data and should be read when the monitor rx data available bit in the status register is set to binary 1 (see sec tion 1.6.2.10.5 ). note that there is no maximum response time requirement to the rx data available flag as the transmission speed is controlled by a hardware handshake mechanism (section 1.7.2 ). 1.6.2.10.5 iom status register/mask register/real time status status register addr = $94 (read only) mask register addr = $96 reset = $00 (write/read) real time status addr = $95 (read only) the bits of the iom status register are defined ac cording to the following table: bit function [0] new ci0 data available [1] new ci1 data available [2] monitor rx data available [3] monitor tx buffer empty [4] monitor rx eof detected [5] monitor rx abort detected [6] monitor tx abort detected [7 ] monitor tx idle the new ci0/ci1 data available bits are set to binary 1 when a change is detected in the ci bus data. the data is read from the appropriate ci receive register (see section 1.6.2.10.6 ). the m onitor rx data available bit is set to binary 1 when a new rx data octet is received in the active monitor channel. the monitor tx buffer empty bit when set to binary 1, indicates that a new octet can be written to the monitor tx register. the monitor rx eof bit is set to binary 1 when an end of file code is detected in the monitor rx channel. the monitor rx abort bit is set to binary 1 when a premature end of file code is detected in the monitor rx channel. this can occur if an incorrect handshake seque nce is detected or the received data is corrupted. the monitor tx abort bit is set to binary 1 when an incorrect handshake sequence is detected or a tx abort command is issued. the monitor tx idle bit, when set to binary 1, indicates when the monitor tra nsmit channel has reached its idle state. the software should wait for the tx idle status before beginning transmission of another monitor channel message. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 45 d/635/2 1.6.2.10.6 ci channel transmit/receive registers transmit: ci0 tx addr = $97 (write/read) ci1 tx addr = $9 8 (write/read) receive: ci0 rx addr = $99 (read only) ci1 rx addr = $9a (read only) the ci0 transmit register is used to set the required 4 bit ci0 data, to control the bac (bus access) bit in the tic channel and to issue an iom timing request (tim ) to an upstream device. the bits are defined in the following table: bit function reset [3:0] ci0 data 1111b [4] bac 0 [6:5] unused - [7] tim 0 the ci0 data is used to transmit 4 bit layer - 1 primitive codes to external layer - 1 devices. the bac bi t is used when the CMX635 is configured as a downstream device. it is transmitted as bit 4 of the tic bus (bit 5 of the last octet of channel 2 in a terminal mode frame). the bac bit is provided to support upstream devices that require bac control. the cmx 635 does not support full tic bus access protocol and cannot be used with other downstream layer - 1 devices on the same iom bus. see section 1.7.2.5 for more details on tic bus operation. the tim bit when set to binary 1, issue s a hardware timing request (iom tx or du pulled low) and is intended for use when the CMX635 is configured as a downstream device. the tim request will persist until either a hardware reset or activity is detected on the iom dcl signal. the ci1 transmit register is used to set the required 6 bit ci1 data and only the 6 lsbs are used. the ci0 receive register contains the latest 4 - bit ci0 value in the 4 lsbs. the msb is set to binary 1 when the same ci0 data has been received in at least 2 consecutive fra mes. the ci1 receive register contains the latest 6 bit ci1 value in the 6 lsbs. the msb is set to binary 1 when the same ci1 data has been received in at least 2 consecutive frames. 1.6.2.11 clock and power control the clock and power control block provides the means to limit power consumption by disabling functions not required for particular applications (or particular modes in the same application). it also provides the necessary status signals to allow ?wake up? from a powered down state. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 46 d/635/2 the clock and pow er block consists of the following registers: clock enable register audio power save register tone power save register status register and mask 1.6.2.11.1 clock enable register addr = $d0 reset = $3f (write/read) the clock enable register allows the master clock to the individual functional blocks to be turned off in order to reduce power consumption. the bits are defined according to the following table: bit function reset [0] iom clk enable 1 [1] st interface clock enable 1 [2] dpll clock enable 1 [3] data routing clock enable 1 [4] hdlc block clock enable 1 [5] speaker phone clock enable 1 [6] unused 0 [7] unused 0 the clocks to the functional blocks are enabled by setting the relevant bit position to binary 1. 1.6.2.11.2 audio enable register addr = $d5 reset = $00 (write/read) the analogue functions of the audio input/output path can be individually enabled or set to a low power state with the audio enable register. the bits are defined according to the following table: bit function reset [0] st transceiver enable 0 [1] input amp rx1 enable 0 [2] input amp rx2 enable 0 [3] earpiece amp tx1 enable 0 [4] speaker amp tx2 enable 0 [5] sidetone amp enable 0 [6] codec enable 0 [7] power save all 0 when set to binary 1 the relevant analogue functional bloc ks are enabled. when set to binary 0 they are set to their low power mode. when bit 7 is set to binary 1 all of the remaining analogue functions are set to their zero power mode. this bit should not be asserted unless all of the other analogue functions a re disabled. note that even when all of the analogue functions are disabled, a small power drain still exists due to the ?wake up? function remaining enabled. setting bit 7 to binary 1 will cause all analogue power drain to be removed, including that due t o the wake - up function. in this mode, activity on the st bus will not generate a wake - up status signal. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 47 d/635/2 1.6.2.11.3 tone enable register addr = $d6 reset = $00 (write/read) the analogue functions of the tone generator/decoder function can be individually enabled or set to a low power state with the tone enable register. the bits are defined according to the following table: bit function reset [0] dtmf decoder enable 0 [1] tone generator enable 0 [2] fsk tone enable 0 [3] ring generator enable 0 [4] spm generat or enable 0 [5] tone/fsk/ring on/off 0 [6] spm on/off 0 [7] unused 0 when set to binary 1 the relevant analogue functional blocks are enabled. when set to binary 0 they are set to their low power mode. note that the tone and fsk outputs cannot be enab led simultaneously. the fsk output has highest priority and will be unconditionally enabled when set to binary 1. the tone output will only be enabled when set to binary 1 and the fsk output is disabled. the ring, tone and fsk signals are turned on when b it 5 is set to binary 1 and off when set to binary 0. the active signal type is selected by the tone or fsk enable bits and, in the case of the ring signal, by selecting the appropriate ring frequency from the tone tables. when controlled from bit 5, the t one signal starts from v bias, and returns to v bias before ending. when fsk mode is enabled, bit 5 initiates fsk transmission. the spm output tone is ramped up to its maximum amplitude when bit 6 is set to binary 1 and ramped down again when set to binary 0 (see section 1.6.2.14.1 ). note that when setting the spm generator to its power save mode after outputting an spm tone, the tone must first be turned off and then sufficient time allowed for the tone to ramp d own to zero amplitude (approx. 4.5ms) before the generator is power saved. 1.6.2.11.4 status/mask registers status addr = $d2 reset = $00 (read only) mask addr = $d1 reset = $00 (write/read) the clock and power status register indicates the presence of iom or st w ake - up signals on the respective busses and reports progress of the iom deactivation sequence. the bits are defined according to the following table: bit function [0] iom wakeup (tim) [1] st wakeup [2] iom deactivated [3] ci0 channel idle [7:4] unuse d the iom wakeup bit when set to binary 1 indicates activity on the iom bus. when the tim interrupt is detected, the software should enable the iom interface by enabling the iom master clock (see section 1.6.2.11.1 ) and enabling the iom block (see section 1.6.2.10.1 ). this will start isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 48 d/635/2 the iom dcl and fsc outputs (timing master mode) and allow ci0 primitives to be exchanged if required. the st wakeup bit when set to bi nary 1 indicates activity on the st bus. it is only required when the st bus and transceiver circuitry is in the power save mode and is used by the software to initiate reactivation of the st bus. the iom deactivated bit when set to binary 1 indicates tha t the iom bus has been completely deactivated functionally and that the master clock to the iom block can be safely disabled. it is intended for use with the iom deactivate state machine (see section 1.6.2.10.1 ) and allows time for all downstream iom devices to deactivate properly before the iom clocks are stopped. if the deactivate state machine is not used this bit will be set to binary 1 as soon as the iom disable command is issued. the ci0 channel idle bit is set to binary 1 when the deactivate state machine is used, when the bac bit of the tic bus is high for 2 consecutive frames and when the ci0 code di (1111b) is being received. the mask register bits, when set to binary 0, will prevent a binary 1 in the c orresponding status register bit position from generating a level - 2 interrupt request (see section 1.6.1 ) to the level - 1 top level status register. 1.6.2.11.5 clock control register addr = $d7 reset = $00 the clock contr ol register enables 12.288mhz or 15.36mhz master crystal mode buffered master clock or 1.536mhz phase locked clock output stopping of master crystal oscillator the bit definition of the clock control register is as follows: bit function [0] stop xtal [1] select master xtal [2] select output clock [7:3] unused when the stop xtal bit is set to binary 1 the master crystal oscillator is disabled. this will set the CMX635 into its lowest power state. the xtal can only be restarted by asserting a hardwar e reset on the device reset pin. when a 15.36mhz master crystal is to be used (possibly for nt configurations) the select master xtal bit should be set to binary 1. when a 12.288mhz crystal is to be used it should be set to binary 0 (default). a buffered version of the master clock is output on the clkout pin (47) when the select output clock bit is set to binary 0. when set to binary 1, the 1.536mhz iom clock is output. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 49 d/635/2 1.6.2.12 speaker phone statistics the speakerphone functions are provided to enable an effi cient hands free speakerphone design to be implemented using the CMX635. the design of speakerphone systems breaks down into two critical functions. the first function gathers statistical data on the transmit and receive data streams in which sufficient d ata processing must be done to separate and identify speech data from background noise on each channel. the CMX635 provides the hardware within the device to carry out these tasks. the second function is an algorithm to decide which channel is dominant (i f any) and partition the overall loop gain between the receive and transmit path so that acoustic feedback is prevented. the software running on the system controller provides this task. the transmit and receive gains are adjusted by writing to the speaker phone attenuation register and the loudspeaker gain register respectively. this approach provides a high degree of latitude to system level designers to create inventive strategies in speakerphone functions whilst relieving the core processor from computat ional tasks at high data rates. all internal digital signal processing is carried out with 24 - bit precision with the most significant 8 bits available to the user. the CMX635 provides the following data processing functions on both the receive and transm it data paths. note that all data processing is done on companded data in both channels. full wave rectification conversion of input data noise filtering of converted data with long time constant (~ 10 s) speech filtering of converted data with fast a ttack time constant (~ 1 ms) and selectable slow decay time constant (128, 256, 500 ms). auto gated noise filter i.e. the statistics integration is suspended when speech is detected in the channel. interrupt control system based upon filter output comparat ors, which provides three interrupt sources for each channel. the interrupt sources are: 1) speech filter output > noise filter output 2) speech filter output > noise filter output + programmable threshold 3) speech filer output > noise filter output + programmable threshold +/ - hysteresis value. interrupt generation when a change in any of the above conditions takes place. the user can poll the indicator flag bits to determine the exact condition that exists within the channel. a hysteresis register t o prevent rapid and spurious interrupts when a slow noisy signal moves close to the integrated background level. the transmit path operates independently on two transmit data streams. one is provided after the attenuation block (see analogue block diagram , section 1.2.2 ) and the other before the attenuator. the pre - attenuated statistics allow the input to be fully characterised when the transmit channel is deemed to be the non - dominant channel, and thus attenuated (or even mut ed). the value of the filtered data in both the noise and speech filter is available to the user, however the filter is updated at the 8khz sample rate and to allow the processor to synchronise to the sample rate an 8khz interrupt is provided. all inte rrupts are maskable. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 50 d/635/2 the registers provided for speakerphone control are: mode register a receive channel and transmit channel threshold register a receive channel and transmit channel hysteresis register a receive channel and transmit channel speech fi lter output register a receive channel and transmit channel noise filter output register status, interrupt status and mask registers 1.6.2.12.1 speakerphone mode register addr = $c0 (write/read) the speakerphone mode register bit allocations are defined in the foll owing table: bit function [1:0] transmit channel speech filter coefficient [2] transmit channel auto integrate mode [4:3] receive channel speech filter coefficient [5] receive channel auto integrate mode [7:6] attenuated channel speech filter coeffic ient the co - efficient codes for bits [1:0], [4:3] and [7:6] are identical and are defined below: code function 00b 127ms discharge time constant 01b 256ms discharge time constant 10b 512ms discharge time constant 11b 1ms charge and discharge time constant bits 2 and 5 control the auto - integrate mode of the respective channels. a binary 1 turns auto - integrate mode on. the auto - integrate function turns off the noise filter integration when speech is detected giving a more accurate noise level. 1.6.2.12.2 rec eive/transmit channel threshold registers receive addr = $c2 (write/read) transmit addr = $c1 (write/read) the receive and transmit threshold registers contain the absolute level above the average noise value that will generate a status1 interrupt (spe ech level > noise + threshold). the threshold level has a magnitude of 6 bits and is contained in register bits [5:0]. bits [7:6] are unused. 1.6.2.12.3 receive/transmit channel hysteresis registers receive addr = $c4 (write/read) transmit addr = $c3 (write/r ead) the receive and transmit hysteresis registers contain the value of the hysteresis level applied to the threshold value (section 1.6.2.12.2 ) before a status 2 interrupt (speech level > noise + threshold h ysteresis) is generated. the hysteresis level has a magnitude of 5 bits and is contained in register bits [4:0]. bits [7:5] are unused. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 51 d/635/2 1.6.2.12.4 receive/transmit/attenuated channel speech filter outputs receive addr = $c6 (read only) transmit addr = $c5 (rea d only) attenuated addr = $c7 (read only) the speech filter registers contain the most significant 8 bits of the 24 - bit speech filter output. the registers can be read asynchronously at any time to obtain the latest value of the speech filter output, o r they can be read synchronously with the 8khz sample clock to enable every speech filter output change to be read. this is achieved through the use of an 8khz sample interrupt (section 1.6.2.12.6 ). the synchro nous read facility may be used where the internal speech detectors are not used and software algorithms are implemented instead. 1.6.2.12.5 receive/transmit channel noise filter outputs receive addr = $c9 (read only) transmit addr = $c8 (read only) the noise fil ter registers contain the most significant 8 bits of the 24 - bit noise filter output. like the speech filter output they can be read synchronously or asynchronously. the noise filter has a fixed symmetrical attack and decay time constant of approximately 10 seconds and is used to determine the background noise level such that speech can be differentiated from it. it can be frozen during detected speech using the auto - integrate function. 1.6.2.12.6 status/interrupt/mask registers status addr = $cc reset = $00 (read ony) interrupt addr = $cb reset = $00 (read only) mask addr = $ca reset = $00 (write/read) the speakerphone interrupt request forms a level - 2 interrupt to the top level status register (section 1.6.1 ) and is derived from the sp interrupt status register. this register indicates whenever a change in state has occurred in the corresponding status register bits (which give a real time indication of the various status inputs). the mask register bits, when set t o binary 0, will prevent a binary 1 in the corresponding interrupt status register bit position from generating a layer - 2 interrupt request. the interrupt status register is cleared to all binary 0s when read by software. the interrupt status register bi ts are defined in the following table: bit function [0] tx status 0 changed state [1] tx status 1changed state [2] tx status 2 changed state [3] rx status 0 changed state [4] rx status 1changed state [5] rx status 2 changed state [6] 8khz sample i nterrupt [7] unused bits [5:0] indicate that there has been a change in state in the corresponding status register bit positions when set to binary 1. change of state refers to either binary 0 to 1 or binary 1 to 0 transitions. bit 6 will be set to bina ry 1 at each reference 8khz sample clock and may be used for synchronous reads of the filter output registers. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 52 d/635/2 the speakerphone status register continuously indicates the current status of the speakerphone functions. the bits are defined as follows: bit function [0] tx status 0 (speech level > noise) [1] tx status 1 (speech level > noise + threshold) [2] tx status 2 (speech level > noise + threshold hysteresis) [3] rx status 0 (speech level > noise) [4] rx status 1 (speech level > noise + threshold ) [5] rx status 2 (speech level > noise + threshold hysteresis) [7:6] unused bits 0 and 3 indicate that the speech filter output is greater than the noise filter output when set to binary 1. this is an indication of detected speech as the speech filt er responds to changes in input much faster than the noise filter. bits 1 and 4 indicate that the speech filter output is greater than the noise filter output plus a programmable threshold value when set to binary 1. this is an alternative indication of s peech where small relative amplitude changes can be ignored. it provides better noise immunity of the speech output. bits 2 and 5 are set to binary 1 when an increasing speech filter output exceeds the noise level by the threshold plus the programmable hy steresis level. they are set to binary 0 when a decreasing speech filter output falls below the threshold less the hysteresis level. this ensures that rapid change of status does not occur for marginal speech signals (when the speech level approaches the n oise level). 1.6.2.12.7 filter reset register addr = $cd (write) a write to this location with the value $01 (lsb = binary 1) will clear and hold clear the 3 voice filter and 2 noise filter registers. the filter registers are released when the reset register is wri tten with $00 (lsb = binary 0). note that only this function and a chip reset will clear the filter register. 1.6.2.13 audio block refer to the analogue block diagram (section 1.2.2 ) for an overview of the audio/tone/codec block. t he audio block contains 3 registers to control the audio path gain and 1 register to control the required routing. the registers available to control the audio path gain and routing functions are: audio rx gain and speakerphone rx attenuation register s peaker output amplifier gain register tone injection attenuation and sidetone attenuation register audio routing register isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 53 d/635/2 1.6.2.13.1 audio rx gain (g1) and speakerphone attenuation (g2) register addr = $f7 reset = $00 (write/read) these two 4 bit gain controls ar e combined into a single register as follows: bits[7:4] g2 gain bits[3:0] g1 gain 0000b 0 db 0000b 0 db 0001b - 3 db 0001b 1.5 db 0010b - 6 db 0010b 3.0 db 0011b - 9 db 0011b 4.5 db 0100b - 12 db 0100b 6.0 db 0101b - 15 db 0101b 7.5 db 0110b - 18 db 0110 b 9.0 db 0111b - 21 db 0111b 10.5 db 1000b - 24 db 1000b 12.0 db 1001b - 27 db 1001b 13.5 db 1010b - 30 db 1010b 15.0 db 1011b - 33 db 1011b 16.5 db 1100b - 36 db 1100b 18.0 db 1101b - 39 db 1101b 19.5 db 1110b - 42 db 1110b 21.0 db 1111b mute 1111b 22.5 db the audio rx gain register (g1) is used to control the second stage of gain required to match the dynamic range of the codec input to the transducer being used. the gain required will vary widely dependent on the configuration (pots or isdn phone) and both the type of microphone being used and the distance from the microphone of the voice source (handset, desk speakerphone, conference speakerphone, etc.). the first stage of gain is provided by the input amplifiers and associated external feedback compo nents. the rx gain register also enables implementation of a software controlled automatic gain control algorithm in conjunction with the data derived from the speakerphone statistics registers. the speakerphone rx attenuation register (g2) provides for programmable attenuation of the input voice signal applied to the codec and is used for speakerphone operation. it includes a complete mute function. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 54 d/635/2 1.6.2.13.2 speaker output amplifier gain register (g3) addr = $f6 reset = $00 (write/read) the speaker amplifier gain register consists of a 3 bit coarse control and a 4 bit fine control plus a mute function as follows: bits[6:4] g3 course gain bits[3:0] g3 fine gain 000b +6 db 0000b 0 db 001b 0 db 0001b - 0.5 db 010b - 6 db 0010b - 1.0 db 011b - 12 db 0011b - 1.5 db 100b - 18 db 0100b - 2.0 db 101b - 24 db 0101b - 2.5 db 110b - 30 db 0110b - 3.0 db 111b - 36 db 0111b - 3.5 db 1000b - 4.0 db 1001b - 4.5 db 1010b - 5.0 db 1011b - 5.5 db 1100b mute 1101b mute 1110b mute 1111b mute bit 7 is unused and sho uld be set to binary 0. the total gain is the addition in dbs of the g3 course and the g3 fine settings. the binary code 01111111b may be used to completely mute the loudspeaker output. the speaker output amplifier gain register adjusts the power output fr om the speaker amplifier. it can be used as a volume control and as a means of attenuating the speaker output for speakerphone operation. for pots configurations, the speaker output is intended for use as the ring input to a slic. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 55 d/635/2 1.6.2.13.3 tone injection attenuat ion (g4) and sidetone attenuation (g5) register addr = $f8 reset = $00 (write/read) these two 4 bit gain controls are combined into a single register as follows: bits[7:4] g5 gain bits[3:0] g4 gain 0000b - 6 db 0000b 0 db 0001b - 8 db 0001b - 3 db 0010b - 10 db 0010b - 6 db 0011b - 12 db 0011b - 9 db 0100b - 14 db 0100b - 12 db 0101b - 16 db 0101b - 15 db 0110b - 18 db 0110b - 18 db 0111b - 20 db 0111b - 21 db 1000b - 22 db 1000b - 24 db 1001b - 24 db 1001b - 27 db 1010b - 26 db 1010b - 30 db 1011b - 28 db 1011b - 33 db 1100b - 30 db 1100b - 36 db 1101b - 32 db 1101b - 39 db 1110b - 34 db 1110b - 42 db 1111b - 36 db 1111b mute the tone injection attenuation register (g4) controls the relative amplitude of the call progress and dtmf comfort tones injected into the ear piece/speaker outputs. it includes a complete mute function. the sidetone attenuation register (g5) allows a programmable level of voice rx data to be injected into the earpiece amplifier path. this emulates the monitor function intrinsic in a pots system . if the sidetone function is not required (i.e. pots configuration), the sidetone amplifier should be disabled (see section 1.6.2.11.2 ). 1.6.2.13.4 audio routing register addr = $f9 reset = $00 (write/read) the audio ro uting register controls the switch functions s1 to s8. the bits are defined in the following table: bit function [0] s1 - microphone input 1 select [1] s2 - rx codec to earpiece output [2] s3 - tone to earpiece output [3] s4 - rx codec to loudspeaker output [4] s5 - tone to loudspeaker output [5] s6 - ring output to loudspeaker output [6] s7 - rx codec to dtmf decoder [7] s8 - tone (dtmf) to tx codec only 1 microphone input at a time may be active. microphone input rx2 is selected when bit 0 is s et to binary 1 and rx1 selected when set to binary 0. the receive codec output is routed to the earpiece summing amplifier, tx1, when bit 1 is set to binary 1. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 56 d/635/2 the tone output is routed to the earpiece summing amplifier, tx1, when bit 2 is set to binar y 1. the relative amplitude of codec and tone signals can be adjusted with g4. the receive codec output is routed to the loudspeaker summing amplifier, tx2, when bit 3 is set to binary 1. the tone output is routed to the loudspeaker summing amplifier, tx2, when bit 4 is set to binary 1. the relative amplitude of codec and tone signals can be adjusted with g4. the ring generator output is routed to the loudspeaker summing amplifier, tx2, when bit 5 is set to binary 1. this function should only be use d for pots configurations, the ring output frequency and waveform being programmed via the tone/codec control register and the tone data register. the input to the dtmf decoder is routed from the receive codec output when bit 6 is set to binary 1 and from the selected microphone input when set to binary 0. in pots configuration the dtmf input should be routed from the microphone input (slic/hybrid output in pots mode) to allow detection of dtmf dialling information from the pots phone. in isdn phone applic ations the dtmf decoder may be routed from the receive codec output to allow implementation of remote control functions using in band dtmf signalling. the input to the transmit codec is switched to the tone generator when bit 7 is set to binary 1. this al lows the isdn phone to transmit in band dtmf tones for remote access systems (menuing systems, answer - phone access etc.). 1.6.2.14 tone/codec block refer to the analogue block diagram (section 1.2.2 ) for an overview of the audio/tone/c odec block. the tone/codec block contains the following functions: tone generation (call progress and dtmf) pcm codec ring tone generation spm generation fsk uart for caller id emulation dtmf decoder the registers available to control the tone functions a re: control register mode register fsk transmit data tone data register dtmf receive data status and mask registers isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 57 d/635/2 1.6.2.14.1 tone/codec control register addr = $f0 reset = $00 (write/read) the control register in the tone/codec block controls the codec enable, t he companding law, and the ring waveform select. the bits are defined according to the following table: bit function [0] select bell fsk mode [1] select asynchronous fsk mode [2] select spm frequency [4:3] ring waveform select [5] codec companding la w [7:6] tone field select the fsk standard is selected with bit 0. bell 202 mode is selected (1200 bps, mark = 1200hz, space = 2200hz) when set to binary 1. v.23 mode is selected (1200 bps, mark = 1300hz, space = 2100hz) when set to binary 0. synchrono us or asynchronous mode of fsk operation is set with bit 1. asynchronous mode is selected when set to binary 1, synchronous mode when set to binary 0. in asynchronous mode the 8 bits from the fsk transmit data register will be transmitted as asynchronous d ata characters at 1200 bps according to the following format and shown in figure 6 : one start bit (space) eight data bits (d0 - d7) with the lsb (d0) transmitted first one stop bit (mark) in synchronous mode, shown in figure 7 , the data bits are transmitted with no start or stop bits. the fsk uart status is indicated in bits 0 (fsk uart data underflow) and bit 1 (fsk uart buffer empty) of the tone status register. data for transmission should be load ed when the buffer empty status is asserted. this status bit indicates when the data in the fsk transmit data register is transferred to the uart for transmission and the data register can be safely reloaded. reloading must occur within approximately 10 bi t periods (8.3ms) for asynchronous mode and 8 bit periods (6.7ms) for synchronous mode if an underflow is to be avoided. if the uart runs out of data, the data underflow status is asserted and the uart will transmit continuous binary 1?s in asynchronous mo de or retransmit the last data in synchronous mode until new data is loaded. fsk transmission is initiated with the ?tone enable? register (see section 1.6.2.11.3 ). fsk transmit data register loaded: digital tx signal: analogue fsk signal: t dly t drdy t fsk t ufl fsk tx data underflow: d0 d0 start start stop d1 d2 d3 d4 d5 d6 d7 d0 start stop d1 d2 d3 d4 d5 d6 d7 figure 6. asynchronous fsk uart operation isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 58 d/635/2 digital tx signal: analogue fsk signal: t dly t drdy t fsk t ufl d0 d0 d0 d1 d1 d2 d2 d3 d3 d4 d4 d5 d5 d6 d6 d7 d7 fsk transmit data register loaded: fsk tx data underflow: figure 7. synchronous fsk uart operation the spm frequency is set with bit 2 of the control register. a binary 1 selects 16khz and a binary 0 selects 12khz. the spm tone is turned on and off with the tone enable register (see section 1.6.2.11.3 ). the spm tone has a rise and fall time each of approximately 4ms. it rises from the bias level to 0dbm in 16 steps of 2db magnitude, and falls from 0dbm to bias level in 16 steps of 2db magnitude. the ring signal is a square, trapezoidal or sinusoidal wave that can be routed to the speaker output through the variable gain of g3. the square and trapezoidal waves are app roximately twice the amplitude of the sinusoidal wave and the gain of the tone injection attenuator (see section 1.6.2.13.3 ) must be adjusted accordingly. the trapezoidal ringing waveform has a crest factor (cf) of 1.35. the ring frequency is set by selecting tone field 0 (bits 6 and 7) and writing the required tone data, in bit field 3 to 0, to the tone data register (see section 1.6.2.14.3 ). the ring waveform is sel ected by bits 4 and 3 according to the following table: code ring waveform 00b square wave 01b trapezoidal 10b sinusoidal 11b unused bit 5 when set to binary 1 selects - law companding. when set to binary 0, a - law companding is selected. the tone s election is accomplished by selecting 1 of 256 tone pair combinations (using the tone data register, section 1.6.2.14.3 ) from 1 of 4 tone fields, giving a choice of 1024 pre - programmed tone combinations. the ton e field is selected by bits 6 and 7 according to the following table: code tone field 00b tone field 0 01b tone field 1 10b tone field 2 11b tone field 3 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 59 d/635/2 1.6.2.14.2 fsk transmit data addr = $f1 reset = $00 (write/read) the fsk transmit data register should b e written with the required 8 bit fsk data when the fsk buffer empty status is set (see section 1.6.2.14.5 ). the data will then be transmitted lsb first according to the format set in the tone/codec control regi ster defined in section 1.6.2.14.1 . 1.6.2.14.3 tone data register addr = $f2 reset = $00 (write/read) the tone data register selects the tone pairs, single tone or ring frequency required from 1 of 4 tone fields. the sel ection codes for each of the tone fields are defined in the following 4 tables: tone field 0, tone/codec control register [7:6] = 00b tx tones register bits 4 - 7 frequency tx tones register bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 252.4 0 0 0 1 * 17.1 0 0 1 0 268.7 0 0 1 0 * 20.5 0 0 1 1 285.3 0 0 1 1 * 24.9 0 1 0 0 315.5 0 1 0 0 * 34.1 0 1 0 1 330.5 0 1 0 1 * 41.0 0 1 1 0 375.2 0 1 1 0 * 51.2 0 1 1 1 404.3 0 1 1 1 - 1 0 0 0 468.0 1 0 0 0 262.9 1 0 0 1 495.8 1 0 0 1 293.6 1 0 1 0 520.6 1 0 1 0 348.2 1 0 1 1 548.0 1 0 1 1 392.6 1 1 0 0 562.8 1 1 0 0 1600 1 1 0 1 578.4 1 1 0 1 1633 1 1 1 0 595.0 1 1 1 0 1827 1 1 1 1 612.5 1 1 1 1 587.2 note: * these outputs are utilised for the ring frequ ency only. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 60 d/635/2 tone field 1, tone/codec control register [7:6] = 01b tx tones register bits 4 - 7 frequency tx tones register bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 120 0 0 0 1 330 0 0 1 0 150 0 0 1 0 416 0 0 1 1 154 0 0 1 1 420 0 1 0 0 250 0 1 0 0 425 0 1 0 1 300 0 1 0 1 433 0 1 1 0 350 0 1 1 0 440 0 1 1 1 360 0 1 1 1 450 1 0 0 0 367 1 0 0 0 460 1 0 0 1 375 1 0 0 1 480 1 0 1 0 380 1 0 1 0 500 1 0 1 1 383 1 0 1 1 600 1 1 0 0 400 1 1 0 0 62 0 1 1 0 1 450 1 1 0 1 720 1 1 1 0 475 1 1 1 0 930 1 1 1 1 480 1 1 1 1 - tone field 2, tone/codec control register [7:6] = 10b tx tones register bits 4 - 7 frequency tx tones register bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = o ff 0 0 0 0 0 = off 0 0 0 1 700 0 0 0 1 700 0 0 1 0 900 0 0 1 0 900 0 0 1 1 1100 0 0 1 1 1100 0 1 0 0 1300 0 1 0 0 1300 0 1 0 1 1500 0 1 0 1 1500 0 1 1 0 1700 0 1 1 0 1700 0 1 1 1 - 0 1 1 1 - 1 0 0 0 950 1 0 0 0 2100 1 0 0 1 1400 1 0 0 1 2225 1 0 1 0 1800 1 0 1 0 - 1 0 1 1 2130 1 0 1 1 2750 1 1 0 0 697 1 1 0 0 1209 1 1 0 1 770 1 1 0 1 1336 1 1 1 0 852 1 1 1 0 1477 1 1 1 1 941 1 1 1 1 1633 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 61 d/635/2 tone field 3, tone/codec control register [7:6] = 11b tx tones register bits 4 - 7 frequency tx tones r egister bits 0 - 3 frequency d7 d6 d5 d4 (hz) d3 d2 d1 d0 (hz) 0 0 0 0 0 = off 0 0 0 0 0 = off 0 0 0 1 540 0 0 0 1 540 0 0 1 0 660 0 0 1 0 660 0 0 1 1 780 0 0 1 1 780 0 1 0 0 900 0 1 0 0 900 0 1 0 1 1020 0 1 0 1 1020 0 1 1 0 1140 0 1 1 0 1140 0 1 1 1 - 0 1 1 1 - 1 0 0 0 1380 1 0 0 0 1380 1 0 0 1 1500 1 0 0 1 1500 1 0 1 0 1620 1 0 1 0 1620 1 0 1 1 1740 1 0 1 1 1740 1 1 0 0 1860 1 1 0 0 1860 1 1 0 1 1980 1 1 0 1 1980 1 1 1 0 - 1 1 1 0 - 1 1 1 1 - 1 1 1 1 - 1.6.2.14.4 dtmf receive data addr = $f5 (read o nly) the dtmf receive data register will contain new decoded dtmf data when the dtmf detected status is set (see 1.6.2.14.5 ). the dtmf state change status will be set whenever a change in state of the dtmf deco der is detected. this can occur when a dtmf tone is detected and also when the dtmf tone ceases. the dtmf detected status will indicate which. the 4 bit dtmf receive data is encoded as follows: dtmf receive data register bits 0 - 3 dtmf tone pairs bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) lower frequency (hz) upper frequency (hz) keypad legend 0 0 0 0 941 1633 d 0 0 0 1 697 1209 1 0 0 1 0 697 1336 2 0 0 1 1 697 1477 3 0 1 0 0 770 1209 4 0 1 0 1 770 1336 5 0 1 1 0 770 1477 6 0 1 1 1 852 1209 7 1 0 0 0 852 1336 8 1 0 0 1 852 1477 9 1 0 1 0 941 1336 0 1 0 1 1 941 1209 * 1 1 0 0 941 1477 # 1 1 0 1 697 1633 a 1 1 1 0 770 1633 b 1 1 1 1 852 1633 c 1.6.2.14.5 tone status/mask registers isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 62 d/635/2 status addr = $f4 reset = $00 (read only) mask addr = $f3 r eset = $00 ( write/read) the tone status register combined with its associated mask register generates a level - 2 interrupt request that forms bit 5 of the top level - 1 status register . the tone status register bits are defined according to the following t able: bit function [3:0] unused [4] dtmf rx tone detected [5] dtmf rx state change [6] fsk tx buffer empty [7] fsk tx data underflow bit 4 will be set to binary 1 when an acceptable quality dtmf tone has been detected. it will be reset to binary 0 when the tone ceases. bit 5 will be set to binary 1 whenever the dtmf state changes (i.e. bit 4 changes from 0 to 1 or from 1 to 0). this can be used to generate an interrupt to indicate the beginning or the end of a detected tone. it is cleared to binary 0 whenever the status register is read. bit 6, when set to binary 1, indicates that the fsk transmit buffer is ready to accept another data byte. bit 7 will be set to binary 1 if the fsk tx buffer is not refreshed before new data is required for trans mission. the mask register bits, when set to binary 0, will prevent a binary 1 in the corresponding status register bit position from generating a level - 2 interrupt request (see section 1.6.1 ) to the level - 1 st atus register . bits 7, 6 and 4 are only cleared to binary 0 when the relevant status changes (i.e. a write to the fsk buffer clears bit 6 and 7, cessation of a dtmf tone clears bit 4). isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 63 d/635/2 1.6.3 register address definition summary address name block $00 d - chann el rx mode register hdlc d rx $01 d - channel rx address match register a1 hdlc d rx $02 d - channel rx address match register a2 hdlc d rx $03 d - channel rx address match register a3 hdlc d rx $04 d - channel rx address match register a4 hdlc d rx $05 d - cha nnel rx address match register b1 hdlc d rx $06 d - channel rx address match register b2 hdlc d rx $07 d - channel rx address match register b3 hdlc d rx $08 d - channel rx address match register b4 hdlc d rx $09 d - channel rx match request register hdlc d rx $0a reserved hdlc d rx $0b d - channel layer - 2 hdlc status register hdlc d rx $0c d - channel layer - 3 hdlc status register hdlc d rx $0d d - channel layer - 2 hdlc status mask register hdlc d rx $0e d - channel layer - 3 hdlc status mask register hdlc d rx $0f d - channel rx octet counter hdlc d rx $10 d - channel tx mode register hdlc d tx $11 reserved hdlc d tx $12 - $13 unused $14 d - channel tx address low register hdlc d tx $15 d - channel tx address high register hdlc d tx $16 d - channel tx frame count registe r hdlc d tx $17 d - channel tx octet count register hdlc d tx $18 - $1f unused $20 b1 - channel rx mode register hdlc b1 rx $21 b1 - channel rx address match register a1 hdlc b1 rx $22 b1 - channel rx address match register a2 hdlc b1 rx $23 b1 - channel rx add ress match register a3 hdlc b1 rx $24 b1 - channel rx address match register a4 hdlc b1 rx $25 b1 - channel rx address match register b1 hdlc b1 rx $26 b1 - channel rx address match register b2 hdlc b1 rx $27 b1 - channel rx address match register b3 hdlc b1 r x $28 b1 - channel rx address match register b4 hdlc b1 rx $29 b1 - channel rx match request register hdlc b1 rx $2a reserved hdlc b1 rx $2b b1 - channel layer - 2 hdlc status register hdlc b1 rx $2c b1 - channel layer - 3 hdlc status register hdlc b1 rx $2d b1 - channel layer - 2 hdlc status mask register hdlc b1 rx $2e b1 - channel layer - 3 hdlc status mask register hdlc b1 rx $2f b1 - channel rx octet counter hdlc b1 rx $30 b1 - channel tx mode register hdlc b1 tx $31 reserved hdlc b1 tx $32 - $33 unused $34 b1 - chan nel tx address low register hdlc b1 tx $35 b1 - channel tx address high register hdlc b1 tx $36 b1 - channel tx frame count register hdlc b1 tx $37 b1 - channel tx octet count register hdlc b1 tx $38 - $3f unused $40 b2 - channel rx mode register hdlc b2 rx $ 41 b2 - channel rx address match register a1 hdlc b2 rx $42 b2 - channel rx address match register a2 hdlc b2 rx isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 64 d/635/2 address name block $43 b2 - channel rx address match register a3 hdlc b2 rx $44 b2 - channel rx address match register a4 hdlc b2 rx $45 b2 - channel rx address match r egister b1 hdlc b2 rx $46 b2 - channel rx address match register b2 hdlc b2 rx $47 b2 - channel rx address match register b3 hdlc b2 rx $48 b2 - channel rx address match register b4 hdlc b2 rx $49 b2 - channel rx match request register hdlc b2 rx $4a reserved hdlc b2 rx $4b b2 - channel layer - 2 hdlc status register hdlc b2 rx $4c b2 - channel layer - 3 hdlc status register hdlc b2 rx $4d b2 - channel layer - 2 hdlc status mask register hdlc b2 rx $4e b2 - channel layer - 3 hdlc status mask register hdlc b2 rx $4f b2 - ch annel rx octet counter hdlc b2 rx $50 b2 - channel tx mode register hdlc b2 tx $51 reserved hdlc b2 tx $52 - $53 unused $54 b2 - channel tx address low register hdlc b2 tx $55 b2 - channel tx address high register hdlc b2 tx $56 b2 - channel tx frame count re gister hdlc b2 tx $57 b2 - channel tx octet count register hdlc b2 tx $58 - $5f unused $60 fifo d tx base address hdlc fifo $61 fifo d rx base address hdlc fifo $62 fifo b1 tx base address hdlc fifo $63 fifo b1 rx base address hdlc fifo $64 fifo b2 tx base address hdlc fifo $65 fifo b2 rx base address hdlc fifo $66 - $67 unused $68 fifo d tx channel write port hdlc fifo $69 fifo b1 tx channel write port hdlc fifo $6a fifo b2 tx channel write port hdlc fifo $6b fifo d rx channel read port hdlc fifo $6c fifo b1 rx channel read port hdlc fifo $6d fifo b2 rx channel read port hdlc fifo $6e fifo clear register hdlc fifo $6f reserved hdlc fifo $70 d tx status register hdlc fifo $71 d rx status register hdlc fifo $72 d tx status mask register hdlc f ifo $73 d rx status mask register hdlc fifo $74 b1 tx status register hdlc fifo $75 b1 rx status register hdlc fifo $76 b1 tx status mask register hdlc fifo $77 b1 rx status mask register hdlc fifo $78 b2 tx status register hdlc fifo $79 b2 rx statu s register hdlc fifo $7a b2 tx status mask register hdlc fifo $7b b2 rx status mask register hdlc fifo $7c - $7d reserved hdlc fifo $7e - $7f unused $80 st control register st interface $81 unused st interface $82 st set - up register st interface isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 65 d/635/2 address name block $83 s t status register st interface $84 interrupt mask register st interface $85 st interrupt register st interface $86 reserved st interface $87 st state machine register st interface $88 state machine mask register st interface $89 multi - frame s registe r st interface $8a multi - frame q register st interface $8b multi - frame status register st interface $8c multi - frame status mask register st interface $8d multi - frame s bit counter st interface $8e reserved st interface $8f unused $90 iom control re gister iom interface $91 iom monitor channel tx register iom interface $92 iom monitor channel control register iom interface $93 iom monitor channel rx register iom interface $94 iom status register iom interface $95 iom real time status iom interfac e $96 iom status mask register iom interface $97 iom ci0 transmit register iom interface $98 iom ci1 transmit register iom interface $99 iom ci0 receive register iom interface $9a iom ci1 receive register iom interface $9b - $9d reserved iom interface $9e - $9f unused $a0 - $a1 reserved dpll $a2 - $af unused $b0 b route control 1 data routing $b1 b route control 2 data routing $b2 b route control 3 data routing $b3 b route control 4 data routing $b4 d route control data routing $b5 reserved data ro uting $b6 - $bf unused $c0 speakerphone mode register speaker - phone $c1 speakerphone transmit channel threshold register speaker - phone $c2 speakerphone receive channel threshold register speaker - phone $c3 speakerphone transmit channel hysteresis regist er speaker - phone $c4 speakerphone receive channel hysteresis register speaker - phone $c5 speakerphone transmit channel speech filter output speaker - phone $c6 speakerphone receive channel speech filter output speaker - phone $c7 speakerphone attenuated cha nnel speech filter output speaker - phone $c8 speakerphone transmit channel noise filter output speaker - phone $c9 speakerphone receive channel noise filter output speaker - phone $ca speakerphone interrupt mask register speaker - phone $cb speakerphone inter rupt status register speaker - phone $cc speakerphone status register speaker - phone $cd speakerphone filter reset speaker - phone $ce - $cf unused $d0 clock enable register clock/power $d1 clock /power status mask register clock/power $d2 clock /power sta tus register clock/power isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 66 d/635/2 address name block $d3 - $d4 reserved clock/power $d5 audio enable register clock/power $d6 tone enable register clock/power $d7 clock control register clock/power $d8 - $df unused $e0 top level status mask register top $e1 top level status regis ter top $e2 - $ef unused $f0 tone/codec control register tone - gen $f1 fsk transmit data tone - gen $f2 tone data register tone - gen $f3 tone status mask register tone - gen $f4 tone status register tone - gen $f5 dtmf receive data tone - gen $f6 speaker outp ut amplifier gain register audio block $f7 audio rx gain and speakerphone attenuation register audio block $f8 tone injection attenuation and sidetone attenuation register audio block $f9 audio routing register audio block $fa - $fd reserved audio block $fe - $ff unused isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 67 d/635/2 1.7 application notes 1.7.1 example CMX635 configurations the following sections give a brief summary of potential applications for the CMX635. 1.7.1.1 dual short loop pots system the following diagram shows how a dual pots system might be implemented . the CMX635 provides all of the required functions to emulate the exchange in a conventional pots system. the slic provides the 4 to 2 wire conversion, ring voltage amplifier, the off - hook detection and the ring trip detection. a cmx625 provides a second fully functional pots port, which is programmed, from the CMX635 via the iom interface. a power supply/control device is required which will generate the high voltage required by the slic (50 - 80 vdc) and the vdd/vss supplies required by the CMX635 and p rocessor. in addition, the power controller may be required to extract power from the s/t bus (power source 1 or "phantom power") or utilise the auxiliary power source 2 input. the power controller must also signal impending power loss to the processor to allow controlled shutdown of both the processor and the data link itself (via an exchange of messages). the power supply must therefore be maintained for a defined period after power loss. figure 8. dual pots configuration s/t u pots slic CMX635 uproc line trans nt1 iom - 2 ring audio out audio in slic control* pots slic cmx625 ring audio out audio in * slic control may be split between up and CMX635 and may include ri ng trip, hook switch, power denial, ring enable. power supply/ control hv hv lv lv lv hv isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 68 d/635/2 s/t u CMX635 key pad uproc line trans nt1 lv power supply/ control lv lcd uart data port hook sw lv 1.7.1.2 isdn telephone/feature/speaker phone. in this configuration the transducers are interfaced directly to the CMX635. the processor will control the display and keypad and will programme the required to nes and amplitudes. in a speakerphone system the processor may also implement the algorithms necessary to control the attenuation of the transmit and receive voice channels to prevent feedback or "howling". to assist in this task, the CMX635 provides stat istics about the amplitude of the voice channels and the background noise. a data port is shown operating through a uart, which may be a simple rs232 device or a more complex usb driver. figure 9. isdn telephone configuration isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 69 d/635/2 1.7.1.3 isdn pc card (active data adaptor) the CMX635 is suited for use in an active, or intelligent data adaptor with a local controlling micro - controller hosting the layer - 3 isdn protocol stack and the low - level de vice drivers for the CMX635 and the data compression algorithms. the CMX635 provides the hdlc layer - 1 and partial layer - 2 interfaces and also provides a voice channel interface. bus interface circuitry is required to interface to the pci bus and would typ ically include dual - port ram, buffering, address control logic etc. this configuration provides high performance data transfer that is not subject to the data ?drop - outs? that can occur with passive data adaptors. s/t u CMX635 uproc line trans nt1 lv power supply/ control lv hook sw lv dual port ram i/f control pci pc bus figure 10. pci c ard configuration isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 70 d/635/2 1.7.1.4 video phone the scheme shown below allows compressed video data to be passed to the CMX635 via the iom - 2 peripheral port. the audio channel is connected to the CMX635 and the digitised data is exported to the audio compressor over the io m - 2 bus. the incoming video is digitised and compressed using a video codec. the compressed audio is routed directly to the video codec where it is combined with the video for transmission over a single b - channel or both b - channels simultaneously. the comb ined compressed video/audio data is re - imported into the CMX635 via the iom interface for transmission over the st bus. figure 11. video phone configuration s/t u audio compression video capture codec CMX635 key pad lcd display uproc line trans nt1 lv power supply/ control lv hook sw lv iom - 2 bus isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 71 d/635/2 1.7.1.5 intelligent nt or nt1plus the CMX635 can be used in a cost effective nt1pl us configuration with the addition of a u interface transceiver and a cmx625 connected via the iom - 2 bus. this system provides 2 fully functional pots lines and an st bus for digital expansion to any te configured isdn equipment. the local processor conta ins the layer - 3 signalling protocol stack and the CMX635 has the capability to share the d - channel with downstream layer - 2 devices. figure 12. nt1 - plus configuration u CMX635 uproc line trans lv power supply/ control lv lv i om - 2 bus u i/f xceiver line trans cmx625 lv s/t hv pots slic ring audio out audio in hv pots slic ring audio out audio in hv isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 72 d/635/2 1.7.2 iom - 2 interface summary 1.7.2.1 general the iom ? - 2 (isdn oriented mo dular revision 2) is an industry standard serial bus for interconnecting telecommunications ic?s. the bus is an evolution of the iom ? interface and is also known as the gci (general circuit interface). the iom - 2 bus provides a symmetrical full duplex comm unication link, containing user data, control/programming and status channels. there are two basic modes of operation known as terminal mode (te mode) and non - terminal mode (non - te or line card mode). the CMX635 operates in te mode and the following descri ption refers to te mode only. the various channels are time multiplexed over a basic four wire serial interface, namely fsc, dcl, dd and du. frames are delimited by an 8khz frame synchronisation clock (fsc), which is generated by the upstream device. the data clock (dcl) clocks data on and off of the data bus (du and dd) and runs at 1.536mhz, which is twice the bit rate. it is always generated by the upstream device. data downstream (dd) receives data from the network. data upstream (du) transmits data to the network. when the bus is deactivated or when data is not being transmitted, dd and du are held in a high impedance state unless the active output feature of the CMX635 is programmed. this allows many downstream iom devices to be connected to the same d d/du bus. 1.7.2.2 frame structure the te mode frame structure consists of 3 sub - frames of 4 bytes each repeated at 8khz, i.e. 96 bits in 125 m s or a data rate of 768kbps. figure 13 shows the te mode frame structure. 125s sub - frame 0 sub - frame 1 sub - frame 2 b1 b2 mon0 c/i0 d m r m x sub - frame 0 ic1 ic2 mon1 c/i1 m r m x sub - frame1 tic sub - frame 2 not used not used not used du/dd fsc dcl m s b l s b fsc = 8khz dcl = 1.536mhz dd, du = 768kbps figure 13. terminal mode frame structure ?sub - frame 0? is used for passing the 2 isdn pcm data channels (b1 and b2), the isdn signalling channel (d) and layer - 1 transceiver control (mon0 and c/i0). isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 73 d/635/2 ?sub - frame 1? is used for passing 2 auxiliary pcm inter - connect channels (ic1 and ic2), an asynchronous programming channel (mon1) and a status indication channel (c/i1). ?sub - frame 2? contains the terminal integrated circuit (tic) bus channel used for arbi trating between multiple layer - 2 d - channel controllers connected on the iom bus. the ?monitor? channels, mon0 and mon1, are identical and have two associated pairs of handshake bits, mx and mr (monitor transmit and receive) that control data flow located in the fourth byte of sub - frames 0 and 1. the handshake procedure utilising the mx and mr bits is described in section 1.7.2.3 . the mon1 byte is used for programming and controlling devices attached to the iom - 2 interface such as the cmx625, isdn ta pots interface. the mon0 byte is used for configuring other layer - 1 devices such a u interface transceiver when the CMX635 is used in nt mode. mon1 channel contention is avoided by a ?speak when spoken to? system whereby the iom s lave devices are given a unique address and only respond when that address is broadcast by the iom master device. the iom slave devices cannot initiate mon1 communication directly in a multi - slave application. each slave must monitor the mon1 channel for i ts unique address in the first byte before processing the following command. each slave can therefore only drive the du mon1 channel when specifically requested to by the master. the ?d? channel consists of two bits located in the fourth byte of sub - frame 0. they provide a 16kbps d - channel data rate for layer - 2 iom devices. the ?command/indicate? channels, c/i0 and c/i1, provide real time status information between devices connected via the iom - 2 bus. the data in these channels is continuously transmitte d, reflecting changes as they occur. the c/i0 channel in sub - frame 0 consists of 4 bits (the other bits being the mx, mr and d - channel ) and the c/i1 channel in sub - frame 1 is 6 bits wide (the other bits being the mr and mx). the c/i0 channel is used to com municate layer - 1 control primitives and is described in more detail in section 1.7.2.4 . the c/i1 channel is shared by all devices on the iom - 2 bus with no mechanism for determining and resolving contention. if multiple slave de vices are expected to drive the c/i1 channel then care must be taken to allocate different bits to each device. an example of c/i1 channel usage would be 6 slave devices each allocated one of the 6 c/i1 bits. when a slave requires attention it asserts its own bit, which is detected by the master as a c/i1 value change (generating a processor interrupt). the processor would then initiate mon1 communications with the appropriate slave and service its request. this is an example of one usage, but the c/i1 bits may be used for any real time command/indicate purpose dependent on system design and number of slaves on the iom - 2 bus. the ?inter - chip communication channels? consists of two 64kbps data channels, ic1 and ic2, and provide additional communications pa ths between iom devices. these channels can be used to route intermediate data between devices. an example is a voice scrambler system where the unscrambled data is passed from an iom codec to an iom scrambler in one of the ic channels and the scrambled da ta is output into a b - channel for transmission by a layer - 1 device. the ?tic? bus is used for connecting more than one layer - 2 device to the d and c/i0 channels in sub - frame 0 and is described in more detail in section 1.7.2.5 . isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 74 d/635/2 1.7.2.3 monitor channel handshake protocol the monitor channel operates on an event driven basis. while data transfers on the bus take place synchronised to the frame sync, the flow of data is controlled by a handshake procedure using the outgoing mx (monitor transmit) and incoming mr (monitor receive) bits. data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted repeatedly (once per 8khz frame) until the transfer is acknowledged (ack) via the mr bit. the actual data rate is not fixed but is dependent upon the response speed of the transmitter and receiver. byte 1 byte 2 byte 3 byte n ack ack ack ack 125s eom mr mx data figure 14. monitor handshake timing (general case) figure 14 shows the general case for monitor handshake timing. the first byte of data is placed on the bus and mx is activated (low). mx remains active and the data remains valid until an inactive - to - active transition of mr is received, indicating that the receiver has read the data off of the bus. the next byte is p laced on the bus after the inactive - to - active transmission of mr, as early as the next frame (there is no limit to the maximum number of frames). at the time that the second byte is transmitted, mx is returned inactive (high) for one frame (mx inactive for more than one frame indicates an end of message). in response to mx going active (low), mr will be deactivated (high) for one frame (the mx inactive to mr inactive delay can be any number of frames). this procedure is repeated for each additional byte. th e transmitter sends an end of message (eom), after the last byte of data has been transmitted, by not reactivating mx after deactivating it. the receiver can hold off the transmitter by keeping mr active until the receiver is ready for the next byte. the transmitter will not start the next transmission cycle until mr goes inactive. the transmitter is able to abort a transmission by holding mx inactive (high) for two or more frames. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 75 d/635/2 figure 15 shows the monitor channel handsha ke procedure. mx = monitor transmit bit, active low. mr = monitor receive bit, active high. md = monitor data figure 15. monitor channel handshake procedure figure 16 shows the maximum speed case for monitor handshake timing. the tr ansmitter can be designed for a higher data throughput than is provided by the general case. the transmitter can deactivate (high) mx and transmit new data one frame after mr is deactivated. in this way, the transmitter is anticipating that mr will be reac tivated one frame after it is deactivated, minimising the delay between bytes. mr being held inactive (high) for two or more frames indicates an abort is being signalled by the receiver. byte 1 byte 2 byte 3 byte n ack ack ack ack eom mr mx data figure 16. monitor handshake timing (maximum spee d case) the abort is a signal from the receiver to the transmitter indicating that data has been missed. the receiver is able to abort a transmission by holding mr inactive (high) for two or more frames in response to mx going active. figure 17 shows a monitor abort request from the receiver. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 76 d/635/2 byte 1 byte 2 abort request eom mr mx data figure 17. abort request from the receiver 1.7.2.4 c/i0 channel description the c/i0 channel in sub - frame 0 is used to pass predefined 4 - bit layer - 1 control primitives betwe en layer - 1 devices. the CMX635 in an nt configuration might use the c/i0 channel to communicate with a u interface transceiver. the predefined codes for nt operation are listed in the following table. c/i0 code dd du 0000 dr tim 0001 res res 0010 tm2 tm2 0011 tm1 tm1 0100 rsy rsy 0101 - - 0110 - - 0111 pu - 1000 ar ar 1001 - - 1010 arl arl 1011 - - 1100 ai ai 1101 - - 1110 ail - 1111 dc di the abbreviations used in the previous table are: ai - activate indication ail - activate indica tion local test loop ar - activation request arl - activation request local test loop dc - deactivation confirmation di - deactivation indication dr - deactivation request pu - power up res - reset rsy - resynchronisation tim - timing request tm1 - test mode 1 tm2 - test mode 2 1.7.2.5 tic bus description isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 77 d/635/2 the tic bus allows multiple layer - 2 devices on the same iom bus to access the d and c/i0 channels. the tic bus is defined as bits[5:2] of the last byte of sub - frame 0. the format for the tic channel in the downstream direction is as follows: 7 6 5 4 3 2 1 0 1 1 s/g 1 1 1 1 1 the stop/go bit s/g when set to binary 1 indicates to downstream layer - 2 devices that the d and/or c/i0 channels are occupied. these devices would then be required to wait until the s/g bit changed to binary 0 before attempting to request d - channel access via the bac/tad mechanism. the s/g bit in the CMX635 when configured as an upstream device is controlled by the d - channel routing and the d - channel access mechanism. if the d - c hannel is routed from the iom bus to the st bus and the st d - channel is free, the s/g bit will be set to binary 0. when the CMX635 is configured as a downstream device the s/g bit input is ignored, thus the CMX635 can be the only downstream layer - 2 device in an nt configuration. the format for the tic channel in the upstream direction is as follows: 7 6 5 4 3 2 1 0 1 1 bac t.a.d. 1 1 bac - bus access bit tad - tic bus address the tic bus in the upstream direction provides a contention resolution mechanism for multiple downstream layer - 2 controllers. the downstream controllers must monitor bac and when it is set to binary 1, the d - channel is available. a downstream controller requiring access to the d - channel will then start to transmit its unique tad, monitoring each bit as it is transmitted. if a contention is detected (tad bit is binary 0 when binary 1 was transmitted) the controller immediately ceases transmission. if the complete tad is transmitted without contention the controller ?occupies? t he d - channel by setting its bac to binary 0. this will hold off other controllers until the d - channel is released (bac set to binary 1). at the end of a transmission, the controller will not attempt to occupy the d - channel until the bac has been at binary 1 for at least 2 consecutive frames, allowing other lower priority controllers access to the channel. the CMX635 does not monitor the tad bits, as this is purely a mechanism for downstream layer - 2 controllers to resolve contention between themselves. the CMX635 can set the bac to binary 0 when configured as a downstream device to allow for upstream devices that require bac activation, however the CMX635 itself has no tic bus arbitration mechanism. the tad bits are not driven and default to binary 1. when the CMX635 is configured as an upstream device with multiple downstream layer - 2 controllers, it can successfully arbitrate d - channel access between itself and the external controllers. when the CMX635 requires access to the d - channel the processor will set up the routing between the hdlc block and the st interface. this will automatically set the s/g bit to binary 1 and prevent access from the external controllers. the data request primitive is then written to the st isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 78 d/635/2 control register (section 1.6.2.1.1 ) and the d - channel access mechanism will arbitrate access with other st layer - 1 devices as normal. if a downstream iom controller requires d - channel access it will issue the ar primitive with the required priority to the cmx63 5 via the c/i0 channel (see section 1.7.2.4 ). the processor will then route the iom d - channel to the st interface and issue the activate request primitive to the st control register. when the d - channel access mechanism determin es that the st d - channel is free, the s/g bit will automatically be set to binary 0 allowing the external controller to complete its tic bus procedure and transmit in the iom d - channel . note that the 4 - bit ci ar codes override most of the other codes and c an be potentially issued by multiple downstream controllers. the CMX635 simply grants access to the iom d - channel . the tic procedure determines which controller has priority. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 79 d/635/2 1.7.3 tone switching when using the tone/fsk on/off bit (bit 5) of the tone enable r egister (section 1.6.2.11.3 ), each tone starts from v bias , and returns to v bias before ending: figure 18. tone starting and stopping when switching between tones in the same column (bits 7 - 4 or bits 3 - 0) of the tone data registe r, section 1.6.2.14.3 ), the transition will be phase continuous. however, switching to the ?off? state will immediately take the output of that tone generator to v bias . figure 19. tone changing the tone data register values that do not have a frequency allocated are indicated by ? - ? in the tone field tables. these values should not be used. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 80 d/635/2 1.7.4 telecom tones the following tables give the hex codes to be programmed into the particular tone field location for various telecommunications s ystems applications. the tables are not exhaustive, but list the more commonly used tones. ringing signals (f 2.5%) field 0 (hz) (hex) off $00 16.7 $01 20 $02 25 $03 35 $04 40 $05 50 $06 on hook ?cpe alert tones single tone field 0 dual ton e field 0 (hz) (hex) (hz) (hex) 375.2 $60 375.2+1827 $6e 404.3 $70 404.3+1827 $7e 468 $80 468+1827 $8e 495.8 $90 495.8+1827 $9e 520.6 $a0 520.6+1827 $ae 548 $b0 548+1827 $be 562.8 $c0 562.8+1827 $ce 578.4 $d0 578.4+1827 $de 1633 $0d nynex (mraa) - amr alert tones (single tone) group a field 0 group b field 0 (hz) (hex) (hz) (hex) 252.4 $10 468 $80 268.7 $20 495.8 $90 285.3 $30 520.6 $a0 315.5 $40 562.8 $c0 330.5 $50 595 $e0 375.2 $60 612.5 $f0 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 81 d/635/2 single frequency call progress tones field 1 (hz) (hex) off $00 120 $10 150 $20 154 $30 250 $40 300 $50 350 $60 400 $c0 425 $04 440 $06 450 $07 480 $09 500 $0a 600 $0b 620 $0c dual frequency call progress tones additive mixing field 1 m ultiplicative field 1 (hz) (hex) mixing (hz) (hex) off $00 350+440 $66 400*16.2 $b2 440+480 $f6 400*20 $a3 480+620 $fc 400*25 $94 400+425 $c4 400*33 $85 400+450 $c7 400*40 $76 425+450 $d4 400*50 $67 425+480 $f4 450*25 $e4 120+620 $1c 600*120 $fd 150+450 $27 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 82 d/635/2 dual tone multi frequency generation field 2 (hz) (hex) off $00 941+1633 $ff 697+1209 $cc 697+1336 $cd 697+1477 $ce 770+1209 $dc 770+1336 $dd 770+1477 $de 852+1209 $ec 852+1336 $ed 852 +1477 $ee 941+1336 $fd 941+1209 $fc 941+1477 $fe 697+1633 $cf 770+1633 $df 852+1633 $ef special information tones, fax and modem tones and customer premises alert tones field 2 (hz) (hex) off $00 950 $80 1100 $30 1300 $ 40 1400 $90 1800 $a0 2100 $08 2225 $09 2130+2750 $bb isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 83 d/635/2 ccitt ?r1? signalling tones field 2 (hz) (hex) 700+900 $12 700+1100 $13 900+1100 $23 700+1300 $14 900+1300 $24 1100+1300 $34 700+1500 $15 900+1500 $25 1100+1500 $35 1300+ 1500 $45 700+1700 $16 900+1700 $26 1100+1700 $36 1300+1700 $46 1500+1700 $56 ccitt ?r2? signalling tones forward mode field 3 backward mode field 3 (hz) (hex) (hz) (hex) off $00 off $00 1380+1500 $89 1140+1020 $65 1380+1620 $8a 114 0+900 $64 1500+1620 $9a 1020+900 $54 1380+1740 $8b 1140+780 $63 1500+1740 $9b 1020+780 $53 1620+1740 $ab 900+780 $43 1380+1860 $8c 1140+660 $62 1500+1860 $9c 1020+660 $52 1620+1860 $ac 900+660 $42 1740+1860 $bc 780+660 $32 1380+1980 $8d 1 140+540 $61 1500+1980 $9d 1020+540 $51 1620+1980 $ad 900+540 $41 1740+1980 $bd 780+540 $31 1860+1980 $cd 660+540 $21 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 84 d/635/2 1.8 performance specification 1.8.1 electrical performance 1.8.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. unit supply (v dd - v ss ) - 0.3 7.0 v voltage on any pin to v ss - 0.3 v dd + 0.3 v current into or out of v dd and v ss pins - 50 +50 ma current into or out of any other pin - 20 +20 ma l4 package min. max. unit total allowable power dissipation at tamb = 25c - 550 mw ... derating - 9.0 mw/c storage temperature - 55 +125 c operating temperature - 40 +85 c 1.8.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. ma x. unit supply (v dd - v ss ) 3.0 5.5 v operating temperature - 40 +85 c isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 85 d/635/2 1.8.1.3 operating characteristics for the following conditions unless otherwise specified: v dd = 3.0v to 5.5v at tamb = - 40 to +85c, 0dbm = 775mvrms = 0dbm0. xtal frequency at nomi nal 12.288mhz or 15.36mhz. details in this section represent design target values and are not currently guaranteed. dc parameters symbol notes min. typ. max. unit i dd all enabled, v dd = 5.0v i dd5a 1, 2 - 43.0 - ma all disabled, v dd = 5.0v i dd5b 1, 3 - 20.0 - a st bus and hdlc only activated, v dd = 5.0v i dd5c 1, 4 - 28.0 - ma + rx1, tx1 and codec, v dd = 5.0v i dd5d 1 - 32.0 - ma + tx2, dtmf rx and tone gen v dd = 5.0v i dd5e 1, 5 - 37.0 - ma all enabled, v dd = 3.3v i dd3a 1, 2 - 24.0 - ma all dis abled, v dd = 3.3v i dd3b 1, 3 - 20.0 - a st bus and hdlc only activated, v dd = 3.3v i dd3c 1, 4 - 16.0 - ma + rx1, tx1 and codec, v dd = 3.3v i dd3d 1 - 18.0 - ma + tx2, dtmf rx and tone gen v dd = 3.3v i dd3e 1, 5 - 22.0 - ma logic input leakage current (vin = 0 to v dd ), i i - 1.0 - +1.0 a logic ?1? input level (cmos inputs) v ih 6 70% - - v dd logic ?0? input level (cmos inputs) v il 6 - - 30% v dd logic ?1? input level (ttl inputs) v ih 6 2.0 - - v logic ?0? input level (ttl inputs), vdd = 3.3 ? 5.5 v v il 6, 7 - - 0.8 v output logic ?1? level dcl,fsc (i oh = 2ma) v oh 8 0.8 - - v dd output logic ?0? level dcl,fsc (i ol = 3ma) v ol 8 - - 0.4 v output logic ?1? level iomtx, iomrx (i oh = 4ma) v oh 8 0.8 - - v dd output logic ?0? level iomtx, iomrx (i ol = 6ma) v ol 8 - - 0.4 v output logic ?1? level ad, clkout (i oh = 3ma) v oh 8 0.8 - - v dd output logic ?0? level ad, clkout (i ol = 4.5ma) v ol 8 - - 0.4 v output logic ?0? level nirq, dtack (i ol = 4.5ma) v ol 8 - - 0.4 v open drain o/ps off state current (v out = v dd ) i odoh - - 1.0 a notes: 1. at 25 c, not including any current drawn from the CMX635 pins by external circuitry. 2. all clocks running, all analogue blocks enabled. 3. master oscillator stopped, all analogue blocks in p ower save mode. 4. no load on tx2, generating and receiving dtmf tones. 5. driving recommended external components with continuous binary 0 (mark). 6. all inputs cmos except iom fsc, dcl, iomrx and iomtx, see signal list. 7. derate linearly minimum ttl logic ?0? leve l from 0.8v at vdd = 3.3v to 0.5v at vdd = 2.7v. 8. all outputs cmos levels. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 86 d/635/2 fsk output notes min. typ. max. unit output of tone generator block (for fsk tones) 9,11 - 1.0 0 1.0 dbm twist (mark level w.r.t. space level) - 2.0 0 +2.0 db tx 1200bits/s ec (v.23 mode) baud rate 1194 1200 1206 baud mark (logical 1) frequency 1297 1300 1303 hz space (logical 0) frequency 2097 2100 2103 hz tx 1200bits/sec (bell 202 mode) baud rate 1194 1200 1206 baud mark (logic al 1) frequency 1197 1200 1203 hz space (logical 0) frequency 2197 2200 2203 hz tone outputs notes min. typ. max. unit output of tone generator block for: 11 single tone 9 - 1.0 0 1.0 dbm dual tone (per tone) 9 - 4.0 - 3.0 - 2.0 dbm dtm f high frequency group 9 - 4.0 - 3.0 - 2.0 dbm dtmf low frequency group 9 - 6.0 - 5.0 - 4.0 dbm tone frequency resolution - 2.5 - 2.5 hz tone output distortion 10 - 0.8 - % notes: 9. at v dd = 5.0v, signal levels are proportional to v dd . 10. frequency above 300hz . 11. see analogue block diagram (section 1.2.2 ) for internal block definition. dtmf decoder notes min. typ. max. unit valid input signal levels (input to dtmf decode block) (each tone of composite signal) 9, 11 - 29.0 - - 2 dbm not decode level (either tone of composite signal) 9 - - - 40.0 dbm twist = high tone/low tone - 9.0 - 10.0 db frequency detect bandwidth 1.8 - 4.5 % dial tone tolerance 12 - - 0 db noise tolerance 12, 13 - - 14.0 - db tone response time 14 - - 40.0 ms tone de - response time 14 - - 45.0 ms tone burst detected 14 40.0 - - ms tone burst ignored 14 - 20.0 - ms pause length detected 14 40.0 - - ms pause length ignored 14 - - 20.0 ms notes: 12. referenced to dtmf tone of lower amplitude. 13. ba ndwidth limited: 0 to 3.4khz gaussian noise. 14. at nominal signal frequencies and without skew. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 87 d/635/2 spm signal level notes min. typ. max. unit level at spm pin 9, 15 - 1.5 0 1.0 dbm tone frequency accuracy - 14.0 - 14.0 hz tone output distortion - 1.2 - % output impedance - 10.0 - k w notes: 15. spm has a soft rise and fall time of about 4ms. the level changes between v bias and 0dbm in 2db steps, 16 steps per rise and fall. when spm is disabled, an extra 4ms falling tail end of signal should be taken into con sideration. pcm codec - filter notes min. typ. max. unit pcm codec - filter (f1) 11 passband 16 300 - 3400 hz passband gain (at 1.02khz) 16 - 3.9 - db passband ripple (w.r.t. gain at 1.02khz) 16 - 0.25 - +0.25 db stopband attenuation (w.r.t. g ain at 1.02khz) 16 30.0 - - db group delay absolute - - 600 s relative to 1khz: 500hz - - 1.5 ms 600hz - - 0.75 ms 2600hz - - 0.25 ms 2800hz - - 1.5 ms signal - to - total distortion ratio as a function of input level (1 khz input level): - 45dbm 17 22.0 - - dbp - 40dbm 17 27.0 - - dbp - 30dbm 17 33.0 - - dbp 0dbm 17 33.0 - - dbp variation of gain with input level (1khz input signal) - 55dbm0 - 3.0 - +3.0 db - 50dbm0 - 1.0 - +1.0 db - 40dbm0 - 0.5 - +0 .5 db +3dbm0 - 0.5 - +0.5 db idle channel noise 17 - - - 65.0 dbm0p notes: 16. meets g.712 specification for analogue - digital attenuation characteristics ( figure 20 ). 17. represents a psophometrically weighted measurement. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 88 d/635/2 200 300 2400 3400 3000 frequency (hz) 0 +0.25 3600 +0.45 +0.9 attenuation (db) -0.25 figure 20. codec filter attenuation characteristics and limits input amplifiers rx1 and rx2 notes min. typ. max. unit open loop gain (i/p ? 1mv at 100hz) - 60.0 - db unity gain bandwidth - 1.0 - mhz input impedance (at 100hz) 10 - - m w minimum impedance on rx1o and rx2o pins 100 - - k w output amplifiers tx1 notes min. typ. max. unit open loop gain (i/p ? 1mv at 100hz) - 40.0 - db unity gain bandwidth - 1.0 - mhz input impedance (at 100hz) 10 - - m w output voltage swing (150 w load at v dd = 5.0v) - 4.2 - vpp output voltage swing (150 w load at v dd = 3.3v) - 2.7 - vpp capacitive load limit - - 100 pf minimum impedance on tx1op pin 100 - - k w output amplifiers tx2 notes min. typ. max. unit output voltage swing (50 w lo ad at v dd = 5.0v) - 3.2 - vpp output voltage swing (50 w load at v dd = 3.3v) - 2.1 - vpp capacitive load limit - - 100 pf power - up timing notes min. typ. max. unit device reset to reliable tone signals at tx1 and spm outputs - 50.0 - ms isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 89 d/635/2 typic al uart timings (see figure 6 and figure 7 ) notes min. typ. max. unit t fsk (delay through the modulator) - 106 - s t dly (1 bit period) - 833 - s t drdy (? bit - period) - 208 - s t ufl (? bit - period) - 625 - s iom - 2 bus timing (see figure 21 ) notes min. typ. max. unit t dcl dcl clock period in te mode - 651 - ns t r / t f dcl clock rise time / fall time 18 - - 20 ns fsc fsc period - 125 - s t fscs fsc set - up time 70 - - ns t fsch fsc hold time 40 - - ns t dudc du delay clock (data out) 18 - - 100 ns t dudf du delay frame (data out) 18 - - 150 ns notes: 18. condition c l = 150pf figure 21. iom - 2 bus timing diagram t t t dcl dcl fscs fsc dudc iomtx (data out) (data in) iomrx bit 0 1st bit t fsch t r t f t dudf isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 90 d/635/2 intel multiplexed style processor bus timing (see figure 22 ) notes min. typ. max. unit 1a t rl read strobe pulse width low 18 170 - - ns 1b t rl read strobe pulse width low 19 270 - - ns 2 t wl write strobe pulse width low 100 - - ns 3 t rc s ncs from read strobe hold 10 - - ns 4 t wcs ncs from write strobe hold 10 - - ns 5 t aw address strobe to write strobe set up 10 - - ns 6 t ar address strobe to read strobe set up 10 - - ns 7 t as address latch enable pulse width 20 - - ns 8 t aas address set up time to address strobe 10 - - ns 9 t aah address hold time from address strobe 10 - - ns 10a t rac read access time from read strobe 18, 20 15 - 220 (250) ns 10b t rac read access time from read strobe 19 15 - 310 ns 11 t rh read data hold time from read strobe 10 - - ns 12 t ws write data setup time to write strobe 10 - - ns 13 t wh write data hold time from write strobe 10 - - ns 14 t csa ncs to address strobe 10 - - ns notes: 19. register access operatio ns in 12.288mhz and 15.36mhz. 20. fifo access operations in 15.36mhz mode only. 21. default values in following table are for 12.288mhz operation. where different, values for 15.36mhz operation are shown in brackets. ncs ad[7:0] ale nwr nrd write read 7 7 8 9 9 10 11 12 13 addr data addr data 14 14 1 2 3 4 5 6 8 figure 22. processor bus tim ing ? intel multiplexed isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 91 d/635/2 motorola multiplexed style processor bus timing (see figure 23 ) notes min. typ. max. unit 1a t ehw e high time for read cycle 18 170 - - ns 1b t ehw e high time for read cycle 19 270 - - ns 2 t ehr e high time for write cycle 100 - - ns 3 t ecs ncs from e hold 0 - - ns 4 t cse ncs to e set up 10 - - ns 5 t ase address strobe to e set up 10 - - ns 6 t as address strobe width 20 - - ns 7 t aas address set up time to as 10 - - ns 8 t aah add ress hold time from as 10 - - ns 9a t rac read access time from e 15 - 220 (250) ns 9b t rac read access time from e 15 - 310 ns 10 t rh read data hold time from e 10 - - ns 11 t ws write data setup time to e 10 - - ns 12 t wh write data hold tim e from e 10 - - ns 13 t rwe r/nw transition to e set up 10 - - ns 14 t csas ncs to address strobe 10 - - ns 15 t rwas r/nw to address strobe 10 - - ns notes: the processor control pins are redefined as follows for a motorola multiplexed style interface: nrd e (pin #11) nwr r/nw (pin #12) ale as (pin #15) ncs ad[7:0] as 1 r/nw e 2 write read 3 3 4 4 5 5 6 6 7 8 8 9 10 11 12 addr data addr da ta 13 14 14 15 7 figure 23. processor bus timing ? motorola multiplexed isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 92 d/635/2 intel non - multiplexed style processor bus timing (see figure 24 ) notes m in. typ. max. unit 1 t csws ncs to nwr setup 21 10 - - ns 2 t cswh ncs from nwr hold 21 10 - - ns 3 t ass asel to nwr setup 10 - - ns 4 t ash asel from nwr hold 10 - - ns 5 t w nwr pulse width 100 - - ns 6a t r nrd pulse width 18 170 - - ns 6a t r nrd pulse width 19 270 - - ns 7 t csrs ncs to nrd setup 21 10 - - ns 8 t csrh ncs from nrd hold 21 10 - - ns 9 t ads indirect address/data set up time to nwr 10 - - ns 10 t adh indirect address/data hold time from nwr 10 - - ns 11a t rac read acce ss time from nrd 18 15 - 220 (250) ns 11b t rac read access time from nrd 19 15 - 310 ns 12 t rh read data hold time from nrd - 22 10 - - ns 13 t ctwr cycle time nwr to nrd for addr wr/rd 23 90 (110) - - ns 14 t ctw cycle time nwr to nwr for addr wr/ wr 23 90 (110) - - ns consecutive reads/writes (see figure 25 ) 15a t cww cycle time nwr to nwr for write - write 18, 24 260 - - ns 15b t cww cycle time nwr to nwr for write - write 19, 24 330 - - ns 16a t crr cycle time nrd to nrd for read - read 18, 24 260 - - ns 16b t crr cycle time nrd to nrd for read - read 19, 24 330 - - ns notes: 22. ncs may be kept low for consecutive writes/reads. 23. time to high impedance. 24. indirect address write followed by a data read or write cycle. 25. consecutive data read/writes using persistent indirect address. figure 24. processor bus timing ? intel non - multiplexed ncs ad[7:0] ale nwr nrd write read 9 10 11 12 indirect addr data data 9 10 9 10 asel indirect addr 1 2 3 4 1 2 3 4 5 6 5 5 7 1 3 2 4 13 14 8 isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 93 d/635/2 ncs ad[7:0] nwr nrd write read data data asel 15 read data data write 16 figure 25. processor bus timing ? consecutive read/writes isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 94 d/635/2 motorola non - multiplexed style processor bus timi ng (see figure 26 below ) notes min. typ. max. unit 1 t css ncs to nds setup 10 - - ns 2 t csawh ncs from nds hold 10 - - ns 3 t aas asel to nds setup 10 - - ns 4 t aah asel from nds hold 10 - - ns 5 t dswa nds pulse width for address write 20 - - ns 6 t dswd nds pulse width for data write 100 - - ns 7 a t dsr nds pulse width for read 18 170 - - ns 7b t dsr nds pulse width for read 19 270 - - ns 8 t as indirect address set up time to nds 10 - - ns 9 t ah indirect address hold time from nds 10 - - ns 10a t rac read access time from nds (reg. read) 18 15 - 220 (250) ns 10b t rac read access time from nds (fifo read) 19 15 - 310 ns 11 t rh read data hold time from ncs 22 10 - - ns 12 t rws r/nw transition to nds setup 0 - - ns 13 t rwh r/nw transition from nds hold 0 - - ns 14 t ctwr cycle time nds to nds for addr wr/rd 23 90 (110) - - ns 15 t ctww cycle time nds to nds for addr wr/wr 23 90 (110) - - ns 16 t ddla dtack delay from nds , address write - - 45 ns 17 t ddha dtack delay from nds , address write - - 45 ns 18 t ddld dtack delay fro m nds , data read/write - - 170 ns 19 t dcsd dtack delay from ncs , data read/write - - 20 ns consecutive reads/writes (see figure 27 below ) 20a t cww cycle time ncs to nds for write - write 18, 24 170 - - ns 20b t cww cycle time ncs to nds for write - write 19, 24 270 - - ns 21a t crr cycle time nds to nds for read - read 18, 24 270 - - ns 21b t crr cycle time nds to nds for read - read 19, 24 330 - - ns notes: the processor control pins are redef ined as follows for a motorola multiplexed style interface: nrd nds (pin #11) nwr r/nw (pin #12) the CMX635 ale pin (#15) should be connected to vss for this mode of operation. isdn subscriber processor CMX635 ? 2001 consumer microcircuits limited 95 d/635/2 ncs ad[7:0] ale r/nw nds write rea d 9 10 11 indirect addr data data 9 8 asel 1 2 3 4 5 7 6 5 14 15 indirect addr dtack 8 8 16 16 17 17 18 19 0 18 19 9 1 3 4 1 1 3 4 3 4 2 2 2 12 13 12 12 13 13 figure 26. processor bus timing ? motorola non - multiple xed ncs ad[7:0] r/nw nds write read data data asel 21 20 read write data data figure 27. processor bus timing ? consecutive reads/writes isdn subscriber processor CMX635 handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to ch ange the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed. oval park - langford maldon - essex cm9 6wg - england telephone: +44 (0)1621 875500 telefax: +44 (0)1621 875600 e - mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk 1.8.2 packaging figure 28. 48 - pin tqfp (l4) mechanical outline cml product data in the process of creating a more global image, the three standard product semiconductor companies of cml microsystems plc (consumer microcircuits limited (uk), mx-com, inc (usa) and cml microcircuits (singapore) pte ltd) have undergone name changes and, whilst maintaining their separate new names (cml microcircuits (uk) ltd, cml microcircuits (usa) inc and cml microcircuits (singapore) pte ltd ), now operate under the single title cml micro- circuits . these companies are all 100% owned operating companies of the cml microsystems plc group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. cml microcircuits product prefix codes until the latter part of 1996, the differentiator between products manufactured and sold from mxcom, inc. and consumer microcircuits limited were denoted by the prefixes mx and fx respectively. these products use the same silicon etc. and today still carry the same prefixes. in the latter part of 1996, both companies adopted the common prefix: cmx. this notification is relevant product information to which it is attached. company contact information is as below: cml microcircuits (uk)ltd communication semiconductors cml microcircuits communication semiconductors cml microcircuits (singapore)pteltd communication semiconductors cml microcircuits (usa) inc. communication semiconductors oval park, langford, maldon, essex, cm9 6wg, england tel: +44 (0)1621 875500 fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com 4800 bethania station road, winston-salem, nc 27105, usa tel: +1 336 744 5050, 0800 638 5577 fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com no 2 kallang pudding road, 09-05/ 06 mactech industrial building, singapore 349307 tel: +65 7450426 fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com d/cml (d)/1 february 2002 |
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